公开(公告)号：US09029928B2

公开(公告)日：2015-05-12

申请号：US13179640

申请日：2011-07-11

申请人： Laurent Marechal ,  Yvon Imbs ,  Romain Coffy

发明人： Laurent Marechal ,  Yvon Imbs ,  Romain Coffy

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L29/40 ,  H01L23/12 ,  H01L23/053 ,  H01L21/56 ,  H01L23/00 ,  H01L23/64 ,  H01L25/16 ,  H01L23/538 ,  H05K1/18

CPC分类号： H01L21/56 ,  H01L21/568 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19105 ,  H05K1/185 ,  H05K2201/10015 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

摘要翻译： 半导体器件包括具有前侧和后侧的晶片。 晶片由至少一个集成电路芯片形成，该集成电路芯片具有与晶片前侧共面的电连接，以及与晶片背面共面的背面。 包括至少一个导电板和电介质板的无源部件位于集成电路芯片附近。 封装块嵌入集成电路芯片和无源部件，该块具有与晶片前侧共面的前侧和与晶片背面共面的背面。 在电连接前端和被动部件之间进行电连接。 该电连接包括放置在晶片正面和晶片背面上的连接线。 电连接还包括至少一个通过封装块的通孔。

公开(公告)号：US20120025348A1

公开(公告)日：2012-02-02

申请号：US13179640

申请日：2011-07-11

申请人： Laurent Marechal ,  Yvon Imbs ,  Romain Coffy

发明人： Laurent Marechal ,  Yvon Imbs ,  Romain Coffy

IPC分类号： H01L23/28 ,  H01L29/92 ,  H01L21/56

CPC分类号： H01L21/56 ,  H01L21/568 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19105 ,  H05K1/185 ,  H05K2201/10015 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

摘要翻译： 半导体器件包括具有前侧和后侧的晶片。 晶片由至少一个集成电路芯片形成，该集成电路芯片具有与晶片前侧共面的电连接，以及与晶片背面共面的背面。 包括至少一个导电板和电介质板的无源部件位于集成电路芯片附近。 封装块嵌入集成电路芯片和无源部件，该块具有与晶片前侧共面的前侧和与晶片背面共面的背面。 在电连接前端和被动部件之间进行电连接。 该电连接包括放置在晶片正面和晶片背面上的连接线。 电连接还包括至少一个通过封装块的通孔。

公开(公告)号：US20110074536A1

公开(公告)日：2011-03-31

申请号：US12890036

申请日：2010-09-24

申请人： Romain Coffy ,  Yvon Imbs ,  Laurent Marechal

发明人： Romain Coffy ,  Yvon Imbs ,  Laurent Marechal

IPC分类号： H01F5/04 ,  H01F7/06

CPC分类号： H01L23/645 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19042 ,  H01L2924/3025 ,  Y10T29/4902 ,  H01L2224/82 ,  H01L2924/00

摘要： An electronic device which includes an electronic component having a substrate and a plurality of metal interconnection layers, the plurality of metal interconnection layers having a top surface. It further comprises a dielectric layer situated above said metal interconnection layers, a conductive layer situated above said dielectric layer, an inductor coil and a ground shield, the inductor coil being formed in the conductive layer and the ground shield being formed in a layer of said plurality of metal interconnection layers.

摘要翻译： 一种电子设备，其包括具有基板和多个金属互连层的电子部件，所述多个金属互连层具有顶表面。 它还包括位于所述金属互连层上方的电介质层，位于所述电介质层上方的导电层，电感线圈和接地屏蔽层，所述电感线圈形成在所述导电层中，所述接地屏蔽形成在所述 多个金属互连层。

公开(公告)号：US08786084B2

公开(公告)日：2014-07-22

申请号：US12751088

申请日：2010-03-31

申请人： Romain Coffy ,  Jean-François Sauty

发明人： Romain Coffy ,  Jean-François Sauty

IPC分类号： H01L23/488 ,  H01L23/00 ,  H01L21/60

CPC分类号： H01L24/85 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/274 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/85375 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01202 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/20752 ,  Y10T29/49126 ,  H01L2224/85 ,  H01L2924/01204 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a bond-wire of a first metallic composition, the bond-wire and the bond-pad being coated with a protection layer of a second metallic composition.

摘要翻译： 半导体封装包括附接到具有导电路径的支撑件的半导体管芯，所述半导体管芯具有通过第一金属组合物的接合线电连接到支撑体上的导电路径上的接合焊盘，所述接合线 并且所述接合垫涂覆有第二金属组合物的保护层。

公开(公告)号：US20130009173A1

公开(公告)日：2013-01-10

申请号：US13531638

申请日：2012-06-25

申请人： Julien Vittu ,  Romain Coffy

发明人： Julien Vittu ,  Romain Coffy

IPC分类号： H01L33/48

CPC分类号： G01S17/026 ,  G01J1/0271 ,  G01J1/0403 ,  G01J1/0407 ,  G01S7/4813 ,  H01L25/167 ,  H01L31/16 ,  H01L33/48 ,  H01L2224/48227 ,  H01L2224/48091 ,  H01L2924/00014

摘要： An electronic package includes a substrate wafer having front and rear faces and a through passage having a front window and a blind cavity communicating laterally with the front window. A receiving integrated circuit chip is mounted on the rear face and includes an optical sensor situated opposite the blind cavity. A transparent encapsulant extends above the optical sensor and at least partially fills the through passage. An emitting integrated circuit chip, embedded in the transparent encapsulant, includes an optical emitter of luminous radiation. The emitting integrated circuit chip may be mounted to the front face or within the through passage to the receiving integrated circuit chip. The substrate wafer may further include a second through passage. The receiving integrated circuit chip further includes a second optical sensor situated opposite the second through passage. A cover plate is mounted to the front face at the second through passage.

摘要翻译： 电子封装包括具有前表面和后表面的基底晶片和具有前窗和与前窗横向连通的盲腔的通孔。 接收集成电路芯片安装在后表面上并且包括位于盲腔相对的光学传感器。 透明密封剂在光学传感器上方延伸并且至少部分地填充通过通道。 嵌入在透明密封剂中的发射集成电路芯片包括发光体的发光体。 发射集成电路芯片可以安装到前面或通向接收集成电路芯片的通路内。 衬底晶片还可以包括第二穿通通道。 接收集成电路芯片还包括与第二贯穿通道相对的第二光学传感器。 盖板在第二通道处被安装到前表面。

公开(公告)号：US20110092000A1

公开(公告)日：2011-04-21

申请号：US12990684

申请日：2009-05-20

申请人： Romain Coffy

发明人： Romain Coffy

IPC分类号： H01L21/66

CPC分类号： G01R31/2884 ,  G01R1/0408 ,  G01R31/2822 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/03 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/11 ,  H01L2924/00

摘要： A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections.

摘要翻译： 一种用于制造和测试集成电路的方法，包括以下步骤：在所述集成电路的上部形成钝化层，所述钝化层包括在所述集成电路的最后一个互连堆叠的金属轨道的水平面处的开口; 在所述开口中形成通过导电轨道部分连接到形成在所述钝化层上的第二焊盘的第一焊盘，所述第一焊盘用于所述集成电路的连接; 通过将测试头与第二个焊盘接触来测试集成电路; 以及消除所述导电轨道部分中的至少一个的至少一部分。

公开(公告)号：US20090134514A1

公开(公告)日：2009-05-28

申请号：US12262982

申请日：2008-10-31

申请人： Romain Coffy ,  Jacky Seiller ,  Gil Provent

发明人： Romain Coffy ,  Jacky Seiller ,  Gil Provent

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H05K3/242 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/11422 ,  H01L2224/11472 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H05K3/3473 ,  H05K2203/043 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01028 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A method for fabricating electrical bonding pads on one face of a wafer includes the production of electrically conductive areas and electrical connection branches connecting these conductive areas. A layer of mask material is deposited and openings are produced in this mask layer which extend above said conductive areas and at least some of which extend at least partly beyond the peripheral edges of the underlying conductive areas. Blocks made of a solder material are produces in the openings by electrodeposition in a bath. The mask material is then removed along with the connection branches. The wafer is passed through or placed in an oven so as to shape, on the conductive areas, the blocks into substantially domed electrical bonding pads.

摘要翻译： 用于在晶片的一个面上制造电接合焊盘的方法包括制造导电区域和连接这些导电区域的电连接分支。 沉积掩模材料层，并且在该掩模层中产生开口，该掩模层在所述导电区域之上延伸，并且至少其中一些延伸至少部分地超过下面的导电区域的周边边缘。 通过在浴中电沉积在开口中产生由焊料材料制成的块。 然后将掩模材料与连接分支一起移除。 将晶片通过或放置在烘箱中，以在导电区域上将块形成为基本上圆顶的电接合焊盘。

公开(公告)号：US20060273813A1

公开(公告)日：2006-12-07

申请号：US11407855

申请日：2006-04-20

申请人： Romain Coffy

发明人： Romain Coffy

IPC分类号： G01R31/02

CPC分类号： H01L23/552 ,  H01L23/055 ,  H01L23/06 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16152 ,  H05K1/0218 ,  H05K3/284 ,  H05K9/0022 ,  H05K2203/041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45015 ,  H01L2924/207

摘要： A device for protecting an electronic circuit comprising a support to which are attached at least two circuit portions, each comprising at least one integrated circuit chip. The device comprises a wafer of a semiconductor material covered with a conductive layer arranged parallel to the support, the wafer being connected to the support by conductive pillars distributed around each circuit portion and in contact with the conductive layer.

摘要翻译： 一种用于保护电子电路的装置，包括支撑件，至少两个电路部分连接至所述支架，每个电路部分包括至少一个集成电路芯片。 该器件包括半导体材料的晶片，该半导体材料被平行于支撑体布置的导电层覆盖，晶片通过分布在每个电路部分周围并与导电层接触的导电柱连接到支撑体。

公开(公告)号：US08928148B2

公开(公告)日：2015-01-06

申请号：US13229924

申请日：2011-09-12

申请人： Romain Coffy ,  Yann Guillou

发明人： Romain Coffy ,  Yann Guillou

IPC分类号： H01L29/72 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/36 ,  H01L23/498 ,  H01L23/00 ,  H01L23/42 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/14519 ,  H01L2224/17519 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A first component includes a slice formed from an integrated circuit chip having a front face and a rear face. An encapsulation block encapsulates the integrated circuit chip such that front and rear faces of the chip and front and rear faces of the encapsulation block are co-planar to form front and rear faces of the slice. Front and rear electrical connection networks are provided on the front and rear faces, respectively, with the electrical connection networks linked by electrical connection vias passing through the encapsulation block. A thermal transfer layer at least partially covers the rear face. A second component may be behind and at a distance from the first component. Connection elements interposed between the first component and the second component include both thermal connection elements in contact with the thermal transfer layer and electrical connection elements interconnecting the first and second components.

摘要翻译： 第一部件包括由具有前表面和后表面的集成电路芯片形成的切片。 封装块封装集成电路芯片，使得芯片的前表面和后表面以及封装块的前后表面是共面的，以形成切片的前后面。 前后电气连接网络分别设置在前表面和后表面上，电连接网络通过通过封装块的电连接通孔连接。 至少部分地覆盖后表面的热转印层。 第二组件可以在第一组件的后面并且距离第一组件一定距离。 插入在第一部件和第二部件之间的连接元件包括与热传递层接触的热连接元件和互连第一和第二部件的电连接元件。

公开(公告)号：US08664044B2

公开(公告)日：2014-03-04

申请号：US13287816

申请日：2011-11-02

申请人： Yonggang Jin ,  Romain Coffy ,  Jerome Teysseyre

发明人： Yonggang Jin ,  Romain Coffy ,  Jerome Teysseyre

IPC分类号： H01L21/00 ,  H01L23/12

CPC分类号： H01L23/498 ,  H01L21/561 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/3114 ,  H01L23/34 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/181 ,  Y10T29/49124 ,  Y10T29/49174 ,  Y10T29/49204 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

摘要： A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.

摘要翻译： 扇出晶片级封装设置有嵌入重构晶片中的半导体管芯。 再分配层位于半导体管芯上方，并且在封装的表面上包括焊盘栅格阵列。 铜管散热器形成在芯片上的再分配层中，与多个配置成将半导体管芯的电路焊盘耦合到焊盘栅极阵列的接触焊盘的多个电迹线相同的层中。 在操作中，散热器提高了从模具到电路板的热传递的效率。