摘要:
A method for preparing a semiconductor with preapplied underfill comprises (a) providing a thinned silicon semiconductor wafer having a plurality of metallic bumps on its active face and, optionally, through-silica-vias vertically through the silicon semiconductor wafer; (b) providing an underfill material on a dicing support tape, in which the underfill material is precut to the shape of the semiconductor wafer; (c) aligning the underfill material on the dicing support tape with the semiconductor wafer and laminating the underfill material to the semiconductor wafer.
摘要:
Multichip packages or multichip modules may include stacked chips and through silicon/substrate vias (TSVs) formed using enclosure-first technology. Enclosure-first technology may include forming an isolation enclosure associated with a TSV early in the fabrication process, without actually forming the associated TSV. The TSV associated with the isolation enclosure is formed later in the fabrication process. The enclosure-first technology allows the isolation enclosures to be used as alignment marks for stacking additional chips. The stacked chips can be connected to each other or to an external circuit such that data input is provided through the bottom-most (or topmost) chip, data is output from the bottom-most (or topmost) chip. The multichip package may provide a serial data connection, and a parallel connection, to each of the stacked chips.
摘要:
A method for making a microelectronic assembly includes providing a microelectronic element 30 with first conductive elements and a dielectric element 50 with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts 40 and other of the first or second conductive elements may include a bond metal 10 disposed between some of the conductive posts 40. An underfill layer 60 may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer 60 and at least deform the bond metal 10. The microelectronic element 30 and the dielectric element 50 can be heated to join them together. The height of the posts 40 above the surface may be at least forty percent of a distance between surfaces of the microelectronic element 30 and dielectric element 50.
摘要:
본 발명은 특정 구조를 갖는 플럭스 활성 경화제를 포함하며, 범프 Chip간 전기적 접속 신뢰성을 만족하고 범프 Chip간 접착층으로써 Cu Bump와 Solder의 산화막을 제거하는 Flux공정이 가능하며, 가열 압착에 따른 Chip Bonding시 Bump와 Solder가 충분히 서로 접속하게 하는 고유동의 반도체용 접착 조성물, 이를 포함하는 접착 필름 및 이를 이용한 반도체 패키지를 제공한다.
摘要:
A microelectronic assembly 100 is provided which includes a first element 110 consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface 103 facing and attached to a major surface 104 of a microelectronic element 102 at which a plurality of conductive pads 106 are exposed, the microelectronic element 102 having active semiconductor devices therein. A first opening 111 extends from an exposed surface 118 of the first element 110 towards the surface 103 attached to the microelectronic element 102, and a second opening 113 extends from the first opening 111 to a first one of the conductive pads 106, wherein where the first and second openings meet, interior surfaces 121, 123 of the first and second openings extend at different angles relative to the major surface 104 of the microelectronic element 102. A conductive element 114 extends within the first and second openings 111, 113 and contacts the at least one conductive pad 106.
摘要:
A microelectronic package (290) having a (substrate 230), a microelectronic element (170), e.g., a chip, and terminals (240) can have conductive elements (238) electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant (201) can overlie the first surface (136) of the substrate and at least a portion of a face (672) of the microelectronic element remote from the substrate, and may have a major surface (200) above the microelectronic element. A plurality of package contacts (120, 220, 408, 410, 427) can overlie a face (672) of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses (410), substantially rigid posts (120, 220), can be electrically interconnected with terminals (240) of the substrate (230), such as through the conductive elements. The package contacts can have top surfaces (121) at least partially exposed at the major (surface 200) of the encapsulant (201).
摘要:
A heterogeneous integrated circuit having at least one tier made of multiple technologies and a method of making the heterogeneous integrated circuit. The heterogeneous integrated circuit includes a package substrate, a first die of a first technology, and a second die of a second technology, where the two dies are located in the same tier. One die can surround the other die. The heterogeneous integrated circuit can also include a wire-bond and/or horizontal micro-bump coupling the two dies. The heterogeneous integrated circuit can also include a wire bond or vertical micro-bump coupling one of the dies to the package substrate. The vertical micro-bump coupling can include a through-via. The two technologies can be any of various technologies including CMOS, glass, sapphire and quartz. One die can also be adjacent to the other die on the same tier and the two dies coupled using a horizontal micro-bump.