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公开(公告)号：US20240173953A1
公开(公告)日：2024-05-30
申请号：US18059993
申请日：2022-11-30
Applicant: Intel Corporation
Inventor： Joshua STACEY , Thomas HEATON , Dilan SENEVIRATNE
CPC classification number: B32B37/0007 , B32B37/02 , B32B37/065 , B32B37/20 , B32B37/30 , B32B2038/0076
Abstract: The present disclosure is directed to an apparatus including a first laminating component configured to laminate a dry film onto a substrate using heat, and a focused cure module configured to selectively cure a first portion of the dry film without curing a second portion of the dry film. The first portion forms a perimeter that surrounds the second portion.
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公开(公告)号：US20230207503A1
公开(公告)日：2023-06-29
申请号：US17561824
申请日：2021-12-24
Applicant: Intel Corporation
Inventor： Jieying KONG , Bainye Francoise ANGOUA , Dilan SENEVIRATNE , Whitney M. BRYKS , Jeremy D. ECTON
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/03 , H01L24/34 , H01L2224/73265 , H01L2924/186 , H01L2924/01029
Abstract: A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate. The metallic contact has a contact surface to make electrical contact with a trace through a dielectric layer over the semiconductor circuit substrate and the metallic contact. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The metallic contact includes a vertical lip extending vertically into the dielectric layer above the contact surface.
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公开(公告)号：US20250112140A1
公开(公告)日：2025-04-03
申请号：US18374609
申请日：2023-09-28
Applicant: Intel Corporation
Inventor： Rahul BHURE , Mitchell PAGE , Joseph PEOPLES , Jieying KONG , Nicholas S. HAEHN , Astitva TRIPATHI , Bainye Francoise ANGOUA , Yosef KORNBLUTH , Daniel ROSALES-YEOMANS , Joshua STACEY , Aaditya Anand CANDADAI , Yonggang Yong LI , Tchefor NDUKUM , Scott COATNEY , Gang DUAN , Jesse JONES , Srinivas Venkata Ramanuja PIETAMBARAM , Dilan SENEVIRATNE , Matthew ANDERSON
IPC: H01L23/498 , H01L23/00 , H01L23/15
Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a core with a first width, and the core comprises a glass layer. In an embodiment, a via is provided through a thickness of the core, where the via is electrically conductive. In an embodiment, a first layer is provided over the core, where the first layer comprises a second width that is smaller than the first width. In an embodiment, a second layer is provided under the core, where the second layer comprises a third width that is smaller than the first width.
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公开(公告)号：US20240217216A1
公开(公告)日：2024-07-04
申请号：US18091028
申请日：2022-12-29
Applicant: INTEL CORPORATION
Inventor： Kristof DARMAWIKARTA , Tarek A. IBRAHIM , Srinivas V. PIETAMBARAM , Dilan SENEVIRATNE , Jieying KONG , Thomas HEATON , Whitney BRYKS , Vinith BEJUGAM , Junxin WANG , Gang DUAN
CPC classification number: B32B17/10642 , B32B7/12 , B32B17/02 , B65D85/48 , B32B2260/04 , B32B2307/202 , B32B2457/00
Abstract: Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.
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公开(公告)号：US20230015619A1
公开(公告)日：2023-01-19
申请号：US17952080
申请日：2022-09-23
Applicant: Intel Corporation
Inventor： Kristof DARMAWAIKARTA , Robert MAY , Sashi KANDANUR , Sri Ranga Sai BOYAPATI , Srinivas PIETAMBARAM , Steve CHO , Jung Kyu HAN , Thomas HEATON , Ali LEHAF , Ravindranadh ELURI , Hiroki TANAKA , Aleksandar ALEKSOV , Dilan SENEVIRATNE
IPC: H01L23/00 , H01L23/522 , H01L21/768
Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).
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Patent Agency Ranking
公开(公告)号：US20250112136A1
公开(公告)日：2025-04-03
申请号：US18374937
申请日：2023-09-29
Applicant: Intel Corporation
Inventor： Bohan SHAN , Jesse JONES , Zhixin XIE , Bai NIE , Shaojiang CHEN , Joshua STACEY , Mitchell PAGE , Brandon C. MARIN , Jeremy D. ECTON , Nicholas S. HAEHN , Astitva TRIPATHI , Yuqin LI , Edvin CETEGEN , Jason M. GAMBA , Jacob VEHONSKY , Jianyong MO , Makoyi WATSON , Shripad GOKHALE , Mine KAYA , Kartik SRINIVASAN , Haobo CHEN , Ziyin LIN , Kyle ARRINGTON , Jose WAIMIN , Ryan CARRAZZONE , Hongxia FENG , Srinivas Venkata Ramanuja PIETAMBARAM , Gang DUAN , Dingying David XU , Hiroki TANAKA , Ashay DANI , Praveen SREERAMAGIRI , Yi LI , Ibrahim EL KHATIB , Aaron GARELICK , Robin MCREE , Hassan AJAMI , Yekan WANG , Andrew JIMENEZ , Jung Kyu HAN , Hanyu SONG , Yonggang Yong LI , Mahdi MOHAMMADIGHALENI , Whitney BRYKS , Shuqi LAI , Jieying KONG , Thomas HEATON , Dilan SENEVIRATNE , Yiqun BAI , Bin MU , Mohit GUPTA , Xiaoying GUO
IPC: H01L23/498 , H01L23/15
Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.
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7.发明公开公开(公告)号：US20230420348A1
公开(公告)日：2023-12-28
申请号：US17852039
申请日：2022-06-28
Applicant: Intel Corporation
Inventor： Jieying KONG , Whitney BRYKS , Dilan SENEVIRATNE , Suddhasattwa NAD , Srinivas V. PIETAMBARAM
IPC: H01L23/498 , H01L21/48
CPC classification number: H01L23/49822 , H01L23/49894 , H01L21/4857 , H01L2224/16225 , H01L24/16
Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer is a dielectric material, and a trace on the first layer. In an embodiment, a pad is on the first layer, and a liner is over the first layer, the trace, and the pad, where a hole is provided through the liner. In an embodiment, the electronic package further comprises a second layer over the first layer, the trace, the pad, and the liner.
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公开(公告)号：US20230086881A1
公开(公告)日：2023-03-23
申请号：US17481247
申请日：2021-09-21
Applicant: Intel Corporation
Inventor： Whitney BRYKS , Jieying KONG , Bainye Francoise ANGOUA , Junxin WANG , Sarah BLYTHE , Ala OMER , Dilan SENEVIRATNE
Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a double-sided glass substrate, to which a PIC is hybrid bonded to a first side of the glass substrate. A die is coupled with the second side of the glass substrate opposite the first side, the PIC and the die are electrically coupled with electrically conductive through glass vias that extend from the first side of the glass substrate to the second side of the glass substrate. Other embodiments may be described and/or claimed.
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公开(公告)号：US20190389179A1
公开(公告)日：2019-12-26
申请号：US16480593
申请日：2017-03-17
Applicant: Intel Corporation
Inventor： Praneeth AKKINEPALLY , Frank TRUONG , Dilan SENEVIRATNE
Abstract: Embodiments are generally directed to dielectric film with pressure sensitive microcapsules of adhesion promoter. An embodiment of an apparatus includes a dielectric film, the dielectric film including a dielectric material layer; a layer of pressure sensitive microcapsules on a first side of the dielectric material layer, the microcapsules including an adhesion promoter; and a cover material on the layer of microcapsules. The pressure sensitive microcapsules are to rupture upon application of a certain rupture pressure.
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公开(公告)号：US20180033707A1
公开(公告)日：2018-02-01
申请号：US15549970
申请日：2015-03-09
Applicant: Intel Corporation
Inventor： Brandon C. MARIN , Trina GHOSH DASTIDAR , Dilan SENEVIRATNE , Yonggang LI , Sirisha CHAVA
CPC classification number: H01L23/14 , H01L21/4846 , H01L23/145 , H01L23/49822 , H01L23/49866 , H01L2224/16227 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2924/15311 , H05K3/062 , H05K3/105 , H05K3/107 , H05K3/182 , H05K3/185 , H05K2201/0209 , H05K2203/107
Abstract: Embodiments of the present disclosure describe selective metallization of an integrated circuit (IC) substrate. In one embodiment, an integrated circuit (IC) substrate may include a dielectric material and metal crystals having a polyhedral shape dispersed in the dielectric material and bonded with a ligand that is to ablate when exposed to laser light such that the metal crystals having the ablated ligand are activated to provide a catalyst for selective electroless deposition of a metal. Other embodiments may be described and/or claimed
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