公开(公告)号：US20230299025A1

公开(公告)日：2023-09-21

申请号：US17890368

申请日：2022-08-18

申请人： Kioxia Corporation

发明人： Yuji Setta

IPC分类号： H01L23/00 ,  H01L23/58 ,  H01L21/02 ,  G03F7/20 ,  H01L27/105

CPC分类号： H01L24/05 ,  H01L23/585 ,  H01L21/02002 ,  H01L24/08 ,  G03F7/20 ,  H01L24/80 ,  H01L27/1052 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/808

摘要： A semiconductor device includes a first device; and a second device bonded to the first device. The first device includes a plurality of first metal pads provided above a semiconductor substrate with an approximately circular shape; a first circuit coupled to at least one of the plurality of the first metal pads; and a first metal ring provided along an outer circumference of the semiconductor substrate to surround the first circuit. The second device includes a plurality of second metal pads joined to the plurality of the first metal pads, respectively; a second circuit coupled to at least one of the plurality of the second metal pads; and a second metal ring joined to the first metal ring.

公开(公告)号：US20230284465A1

公开(公告)日：2023-09-07

申请号：US18111287

申请日：2023-02-17

申请人： Micron Technology, Inc.

发明人： Hernan A. Castro ,  Kunal R. Parekh

IPC分类号： H10B80/00 ,  H01L23/48 ,  H01L23/00

CPC分类号： H10B80/00 ,  H01L23/481 ,  H01L24/08 ,  H01L24/94 ,  H01L24/80 ,  H01L2224/08146 ,  H01L2224/94 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L24/05 ,  H01L2224/80379

摘要： Semiconductor die stacks and associated systems and methods are disclosed. In an embodiment, a semiconductor die stack corresponds to a pair of a logic die and a memory die directly bonded together. The logic die includes integrated circuits generated by relatively high temperature process steps whereas the memory die includes memory cells with materials generated using relatively low temperature process steps. A logic wafer including the logic dies and a memory wafer including the memory dies are separately fabricated. Subsequently, the logic wafer and the memory wafer are directly bonded to generate the semiconductor die stacks. Either the logic dies or the memory dies include through-substrate vias (TSVs) to provide power and signals for the semiconductor die stacks. The resulting semiconductor devices operate as a single device as if they were formed in a monolithic substrate.

公开(公告)号：US20230282650A1

公开(公告)日：2023-09-07

申请号：US17973814

申请日：2022-10-26

申请人： Samsung Display Co., LTD.

发明人： Dae Hwan JANG ,  Seok Hyun NAM ,  Jin Ho CHO

IPC分类号： H01L27/12 ,  H01L25/16 ,  H01L33/36 ,  H01L23/00

CPC分类号： H01L27/124 ,  H01L25/167 ,  H01L33/36 ,  H01L27/1288 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/05582 ,  H01L2224/05557 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/0807 ,  H01L2224/08155

摘要： A display device comprises a substrate comprising a first contact hole, a barrier insulating layer disposed on the substrate and comprising a second contact hole, a fan-out line disposed in a first metal layer on the barrier insulating layer and comprising a pad part inserted into the second contact hole, a display layer disposed on the fan-out line, and a flexible film disposed below the substrate and having a lead electrode which is inserted into the first contact hole and bonded to the pad part. The pad part comprises a first base, a first protrusion integral with the first base and protruding from the first base, and a second protrusion protruding from the first protrusion.

公开(公告)号：US20230282582A1

公开(公告)日：2023-09-07

申请号：US18196077

申请日：2023-05-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ju-Il CHOI ,  Gyuho KANG ,  Seong-Hoon BAE ,  Dongjoon OH ,  Chungsun LEE ,  Hyunsu HWANG

IPC分类号： H01L23/532 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L23/53238 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/16227

摘要： A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

公开(公告)号：US20230282528A1

公开(公告)日：2023-09-07

申请号：US17897729

申请日：2022-08-29

申请人： Samsung Electronics Co., Ltd.

发明人： Ju Bin SEO ,  Su Jeong PARK ,  Seok Ho KIM ,  Kwang Jin MOON

IPC分类号： H01L21/66 ,  H01L23/00

CPC分类号： H01L22/32 ,  H01L24/08 ,  H01L24/06 ,  H01L24/05 ,  H01L2224/08145 ,  H01L2224/06515 ,  H01L2224/05647 ,  H01L2224/05147 ,  H01L2224/80379 ,  H01L2924/05042 ,  H01L24/80

摘要： A semiconductor package is provided. The semiconductor package includes a first semiconductor substrate, a first semiconductor element layer on an upper surface of the first semiconductor substrate, a first wiring structure on the first semiconductor element layer, a first connecting pad connected to the first wiring structure, a first test pad connected to the first wiring structure, a first front side bonding pad connected to the first connecting pad and including copper (Cu), and a second front side bonding pad connected to the first front side bonding pad and including copper (Cu) which has a nanotwin crystal structure different from a crystal structure of copper (Cu) included in the first front side bonding pad, wherein a width of the first front side bonding pad in the horizontal direction is different from a width of the second front side bonding pad in the horizontal direction.

公开(公告)号：US20230275047A1

公开(公告)日：2023-08-31

申请号：US17661154

申请日：2022-04-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Jen Chen ,  Wei-Chun Pai ,  Cheng Wei Ho ,  Sheng-Huan Chiu

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L24/05 ,  H01L24/94 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L24/04 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05569 ,  H01L24/06 ,  H01L2224/06138 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L24/11 ,  H01L2224/1146 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13124 ,  H01L24/16 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L24/81 ,  H01L2224/81801 ,  H01L24/32 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L24/92 ,  H01L2224/92125 ,  H01L2224/94

摘要： A method includes forming a first polymer layer over a plurality of metal pads, and patterning the first polymer layer to forming a plurality of openings in the first polymer layer. The plurality of metal pads are exposed through the plurality of openings. A plurality of conductive vias are formed in the plurality of openings. A plurality of conductive pads are formed over and contacting the plurality of conductive vias. A conductive pad in the plurality of conductive pads is laterally shifted from a conductive via directly underlying, and in physical contact with, the conductive pad. A second polymer layer is formed to cover and in physical contact with the plurality of conductive pads.

公开(公告)号：US20230268299A1

公开(公告)日：2023-08-24

申请号：US18020349

申请日：2021-11-16

申请人： SIPLP MICROELECTRONICS (CHONGQING) CO., LTD.

发明人： Weiyuan YANG

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L21/56

CPC分类号： H01L24/05 ,  H01L23/295 ,  H01L24/03 ,  H01L21/565 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05572 ,  H01L2224/0391

摘要： The present disclosure provides a die, a manufacturing method of the die, a chip packaging structure and a manufacturing method of the chip packing structure. The die includes an aluminum bonding pad, a passivation layer and a copper layer. The aluminum bonding pad and the passivation layer are both on an active surface of the die, and the passivation layer has a first opening in which the aluminum bonding pad is partially exposed. The copper layer is on the aluminum bonding pad and covers a part of the aluminum bonding pad. A boundary of the copper layer is spaced apart from the passivation layer at a boundary of the first opening by a distance. Since the copper layer covers a part of the aluminum bonding pad, and the boundary of the copper layer is spaced apart from the passivation layer by a distance, the copper layer is completely received in the opening in the passivation layer.

公开(公告)号：US11728296B2

公开(公告)日：2023-08-15

申请号：US17073533

申请日：2020-10-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiao Yun Lo ,  Lin-Chih Huang ,  Tasi-Jung Wu ,  Hsin-Yu Chen ,  Yung-Chi Lin ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L23/00 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/03462 ,  H01L2224/03602 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05565 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/1145 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/131 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2224/05187 ,  H01L2924/04941 ,  H01L2224/05187 ,  H01L2924/04953 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/03602 ,  H01L2924/00014 ,  H01L2224/03614 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014

摘要： A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

公开(公告)号：US20230253358A1

公开(公告)日：2023-08-10

申请号：US18302935

申请日：2023-04-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sheng-Yu Wu ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC分类号： H01L23/00 ,  H01L23/498 ,  H05K1/11 ,  H01L25/10 ,  H01L29/66 ,  H01L25/065 ,  H01L23/528

CPC分类号： H01L24/17 ,  H01L23/528 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/09 ,  H01L24/14 ,  H01L24/16 ,  H01L24/33 ,  H01L24/81 ,  H01L25/105 ,  H01L25/0657 ,  H01L29/66 ,  H05K1/111 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0235 ,  H01L2224/0401 ,  H01L2224/1308 ,  H01L2224/02375 ,  H01L2224/3003 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14133 ,  H01L2224/16013 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2225/1047 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/35121 ,  H05K2201/09727 ,  H05K2201/10674

摘要： A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.

公开(公告)号：US11715677B2

公开(公告)日：2023-08-01

申请号：US17234525

申请日：2021-04-19

申请人： STMicroelectronics, Inc.

发明人： Jefferson Sismundo Talledo ,  Rammil Seguido

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L23/49531 ,  H01L21/563 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L21/561 ,  H01L23/3107 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4918 ,  H01L2224/73265 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2224/45139 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014

摘要： A semiconductor device includes a substrate that includes an opening extending through a thickness of the substrate, a frame that includes an integrated circuit (IC) die pad in the opening and a plurality of arms extending outwardly from the IC die pad, an IC mounted on the IC die pad, a plurality of bonding elements electrically coupling the substrate with the IC without the frame being an intermediary coupling element, and an encapsulant surrounding the IC, the plurality of bonding elements, and the plurality of arms. The substrate has a first major surface and a second major surface. Each arm is devoid of a contact pad. Each arm has a distal end coupled to the first major surface of the substrate, and each arm has a proximal end disposed over the first major surface of the substrate.