公开(公告)号：US20070166993A1

公开(公告)日：2007-07-19

申请号：US11685216

申请日：2007-03-13

Applicant: Jin-Yuan Lee ,  Chien-Kang Chou ,  Shih-Hsiung Lin ,  Hsi-Shan Kuo

Inventor： Jin-Yuan Lee ,  Chien-Kang Chou ,  Shih-Hsiung Lin ,  Hsi-Shan Kuo

IPC: H01L21/44

CPC classification number: H01L25/0657 ,  H01L24/11 ,  H01L24/13 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/013

Abstract: A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.

Abstract translation: 圆柱形粘结结构及其制造方法。 在硅芯片的接合焊盘上形成圆柱形接合结构，并且在形成倒装芯片封装的过程中将芯片翻转以与衬底板连接。 圆柱形接合结构主要包括导电柱和焊帽。 导电柱形成在硅芯片的接合焊盘上，并且焊接帽附接到导电柱的上端。 焊锡帽的熔点低于导电柱。 焊帽可以被配置成圆柱形，球形或半球形。 为了制造圆柱形接合结构，在硅晶片上形成具有与位于晶片上的接合焊盘相对应的多个开口的图案化掩模层。 导电材料沉积到开口中以形成导电柱，最后在每个导电柱的末端附着焊帽。

公开(公告)号：US20070152328A1

公开(公告)日：2007-07-05

申请号：US11323526

申请日：2005-12-29

Applicant: Susheel Jadhav ,  Daoqiang Lu ,  Nitin Deshpande

Inventor： Susheel Jadhav ,  Daoqiang Lu ,  Nitin Deshpande

IPC: H01L21/76

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13609 ,  H01L2224/75 ,  H01L2224/75314 ,  H01L2224/757 ,  H01L2224/7598 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/29099 ,  H01L2924/00

Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a plurality of first metal bumps on a first surface, and a plurality of second metal bumps on a second surface, wherein at least one of (i) the plurality of first metal bumps, and (ii) the plurality of second metal bumps, comprises a solder. The method also includes forming a metal region including indium and tin, on at least one of (i) the plurality of first metal bumps, and (ii) the plurality of second metal bumps. The method also includes positioning the first metal bumps on the second metal bumps, and heating the metal bumps and the metal region and melting the solder. Other embodiments are described and claimed.

Abstract translation: 描述了用于制造电子设备的电子设备和方法。 一种方法包括在第一表面上设置多个第一金属凸块，以及在第二表面上设置多个第二金属凸块，其中，（i）多个第一金属凸块中的至少一个，以及（ii）多个第二金属凸块 金属凸块，包括焊料。 该方法还包括在（i）多个第一金属凸块和（ii）多个第二金属凸块中的至少一个上形成包括铟和锡的金属区域。 该方法还包括将第一金属凸块定位在第二金属凸块上，并加热金属凸块和金属区域并熔化焊料。 描述和要求保护其他实施例。

公开(公告)号：US07227263B2

公开(公告)日：2007-06-05

申请号：US10995411

申请日：2004-11-24

Applicant: Tadashi Yamaguchi

Inventor： Tadashi Yamaguchi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13609 ,  H01L2224/274 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip which has a top surface, a conductive member which includes a first portion which is located on the electrode pad and a second portion which is extended from the first portion, and a sealing resin which seals the top surface of the semiconductor chip and the conductive member. A top surface of the second portion is exposed from the sealing resin and a part of the top surface of the second portion is concaved from a surface of the sealing resin. An external electrode is formed on the top surface of the second portion.

Abstract translation: 半导体器件包括具有顶表面的半导体芯片，包括位于电极焊盘上的第一部分和从第一部分延伸的第二部分的导电部件和密封树脂， 半导体芯片和导电构件。 第二部分的顶表面从密封树脂露出，并且第二部分的顶表面的一部分从密封树脂的表面凹陷。 外部电极形成在第二部分的顶表面上。

公开(公告)号：US20070120241A1

公开(公告)日：2007-05-31

申请号：US11329883

申请日：2006-01-10

Applicant: John Trezza ,  Ross Frushour

Inventor： John Trezza ,  Ross Frushour

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/1358 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/24226 ,  H01L2224/45111 ,  H01L2224/75 ,  H01L2224/75305 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81825 ,  H01L2224/81894 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/183 ,  H01S5/18308 ,  H01S2301/176 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An apparatus for use with multiple chips having multiple posts as to engage at least a portion of a surface of one of the multiple chips, a frame configured to releasably constrain each of the posts so that, when unconstrained, each individual post can contact an individual chip and, when constrained, will allow a uniform vertical force to be applied to the chips.

Abstract translation: 一种用于具有多个芯片的多个芯片的装置，用于接合所述多个芯片中的一个芯片的表面的至少一部分，框架，其被配置为可释放地约束每个所述柱，使得当不受约束时，每个单独的柱可以接触个体 并且当被约束时将允许将均匀的垂直力施加到芯片。

公开(公告)号：US20070020912A1

公开(公告)日：2007-01-25

申请号：US11519153

申请日：2006-09-12

Applicant: Tomohiro Nishiyama ,  Masamoto Tago

Inventor： Tomohiro Nishiyama ,  Masamoto Tago

IPC: H01L21/44

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/8191 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H05K2201/0367 ,  H05K2201/2081 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2224/29099

Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Abstract translation: 在半导体芯片的布线膜上通过互连膜和晶片单元中的粘合膜形成由铜等形成的柱状凸起，其中电解电镀可以进行封装形成。 氧化防止膜在上表面或上表面和侧表面的一部分上由金形成。 根据需要，在柱状凸起面上形成氧化膜等防湿膜。 如果将该凸块焊接到封装基板上的焊盘，则焊料在柱状凸起上表面的整个区域和侧表面的一部分中变湿。 可以形成稳定且可靠的接合形式。 此外，由于柱状凸块不熔合，所以半导体基板与封装基板之间的距离不会被焊料变窄。

公开(公告)号：US20060292824A1

公开(公告)日：2006-12-28

申请号：US11448598

申请日：2006-06-07

Applicant: Eric Beyne ,  Riet Labie

Inventor： Eric Beyne ,  Riet Labie

IPC: H01L29/82 ,  H01L21/30

CPC classification number: H01L24/11 ,  B81C1/00333 ,  H01L21/4846 ,  H01L21/563 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13157 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/29111 ,  H01L2224/73203 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/81948 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/9211 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/00

Abstract: One inventive aspect is related to a method of bonding two elements. The method comprises producing on a first element a first micropattern, comprising a first metal layer. The method further comprises producing on a second element a second micropattern, comprising a second metal layer. The method further comprises applying onto the first micropattern and/or on the second micropattern a layer of solder material. The method further comprises producing on at least one of the elements a patterned non-conductive adhesive layer around the micropattern on the element. The method further comprises joining the first micropattern and the second micropattern by means of a thermocompression or reflow method, wherein the producing of an adhesive layer is performed before the joining such that the first and second elements are secured to each other by the adhesive layer(s) after joining.

公开(公告)号：US20060278986A1

公开(公告)日：2006-12-14

申请号：US11329952

申请日：2006-01-10

Applicant: John Trezza

Inventor： John Trezza

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/11 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/1358 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.

Abstract translation: 一种制造半导体芯片的方法，该半导体芯片具有衬底，与衬底相邻的掺杂半导体材料和在掺杂半导体材料的外侧的器件焊盘，包括通过至少部分衬底产生通孔，所述通孔具有外围和 在足够的位置和深度处的底部，以使通孔靠近设备衬垫，但是物理地与器件衬垫隔开，将导电材料引入通孔，并将导电材料连接到信号源，使得信号 将有意地从导电材料传播到器件焊盘，而不会在导电材料和器件焊盘之间存在任何直接的电连接。

公开(公告)号：US20060278981A1

公开(公告)日：2006-12-14

申请号：US11329885

申请日：2006-01-10

Applicant: John Trezza ,  John Callahan ,  Gregory Dudoff

Inventor： John Trezza ,  John Callahan ,  Gregory Dudoff

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L24/11 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2224/75315 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip contact functionally having an IC pad, a barrier layer over the IC pad, and a malleable material over the barrier layer. An alternative chip contact functionally having an IC pad, a barrier layer over the IC pad, and a rigid material over the barrier layer.

Abstract translation: 芯片接触器在功能上具有IC焊盘，IC焊盘上的阻挡层，以及在阻挡层上方的可延展材料。 替代的芯片接触器在功能上具有IC焊盘，IC焊盘上的阻挡层以及阻挡层上的刚性材料。

公开(公告)号：US20060278966A1

公开(公告)日：2006-12-14

申请号：US11329874

申请日：2006-01-10

Applicant: John Trezza ,  John Callahan ,  Gregory Dudoff

Inventor： John Trezza ,  John Callahan ,  Gregory Dudoff

IPC: H01L23/02

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/488 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11912 ,  H01L2224/13012 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/1358 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/24226 ,  H01L2224/45111 ,  H01L2224/75 ,  H01L2224/75305 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81825 ,  H01L2224/81894 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/183 ,  H01S5/18308 ,  H01S2301/176 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electrical connection between two chips includes an IC pad on a first chip, an IC pad on a second chip, a first barrier metal over the IC pad of the first chip, a second barrier metal over the IC pad of the second chip, a malleable electrically conductive metal, different from the barrier metals, trapped between the first barrier metal and the second barrier metal, the first barrier metal, the malleable conductive metal and the second barrier metal forming a complete electrically conductive path between the IC pad of the first chip and the IC pad of the second chip.

公开(公告)号：US07135770B2

公开(公告)日：2006-11-14

申请号：US10359124

申请日：2003-02-06

Applicant: Tomohiro Nishiyama ,  Masamoto Tago

Inventor： Tomohiro Nishiyama ,  Masamoto Tago

IPC: H01L23/28

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11901 ,  H01L2224/11906 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/8191 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H05K2201/0367 ,  H05K2201/2081 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2224/29099

Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Abstract translation: 在半导体芯片的布线膜上通过互连膜和晶片单元中的粘合膜形成由铜等形成的柱状凸起，其中电解电镀可以进行封装形成。 氧化防止膜在上表面或上表面和侧表面的一部分上由金形成。 根据需要，在柱状凸起面上形成氧化膜等防湿膜。 如果将该凸块焊接到封装基板上的焊盘，则焊料在柱状凸起上表面的整个区域和侧表面的一部分中变湿。 可以形成稳定且可靠的接合形式。 此外，由于柱状凸块不熔合，所以半导体基板与封装基板之间的距离不会被焊料变窄。