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    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    185.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 审中-公开
    芯片包装及其形成方法

    公开(公告)号：US20160233260A1

    公开(公告)日：2016-08-11

    申请号：US15013135

    申请日：2016-02-02

    Applicant: XINTEC INC.

    Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU

    IPC: H01L27/146 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/0216

    CPC classification number: H01L27/14636 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/02327 ,  H01L31/1868 ,  H01L2224/11

    Abstract: An embodiment of the invention provides a chip package which includes a first substrate including a device region and having a first surface and a second surface opposite thereto. A dielectric layer is disposed on the second surface of the first substrate and includes a conducting pad structure connected to the device region, and the first substrate completely covers the conducting pad structure. A second substrate is disposed on the second surface of the first substrate and the dielectric layer is located between the first substrate and the second substrate. The second substrate has a first opening exposing a surface of the conducting pad structure, and a redistribution layer is conformally disposed on a sidewall of the first opening and the surface of the exposed conducting pad structure. A method for forming the chip package is also provided.

    Abstract translation: 本发明的一个实施例提供一种芯片封装，其包括包括器件区域并具有第一表面和与其相对的第二表面的第一衬底。 电介质层设置在第一衬底的第二表面上，并且包括连接到器件区域的导电焊盘结构，并且第一衬底完全覆盖导电焊盘结构。 第二基板设置在第一基板的第二表面上，并且电介质层位于第一基板和第二基板之间。 第二基板具有暴露导电焊盘结构的表面的第一开口，并且再分配层保形地设置在第一开口的侧壁和暴露的导电焊盘结构的表面上。 还提供了一种用于形成芯片封装的方法。

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    186.
    发明申请
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开
    芯片包装及其制造方法

    公开(公告)号：US20160211297A1

    公开(公告)日：2016-07-21

    申请号：US15001065

    申请日：2016-01-19

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu LIU ,  Chia-Ming CHENG

    IPC: H01L27/146

    Abstract: A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.

    Abstract translation: 芯片封装的制造方法包括以下步骤。 透光基板结合到晶片的第一表面，使得透光基板和晶片之间的阻挡元件覆盖晶片的导电焊盘。 蚀刻晶片背离第一表面的第二表面，使得在晶片中同时形成中空区域和选择性地与中空区域连通的沟槽。 蚀刻导电焊盘上的第一隔离层，以通过中空区域露出导电焊盘。

    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    188.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
    芯片包装及其制造方法

    公开(公告)号：US20160204061A1

    公开(公告)日：2016-07-14

    申请号：US14992776

    申请日：2016-01-11

    Applicant: XINTEC INC.

    Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE

    IPC: H01L23/522 ,  H01L21/304 ,  H01L21/268 ,  H01L21/76 ,  H01L21/78 ,  H01L21/683 ,  H01L21/768 ,  H01L23/528

    CPC classification number: H01L23/5226 ,  G06K9/0002 ,  H01L21/268 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5283 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A chip package including a chip, a first though hole, a conductive structure, a first isolation layer, a second though hole and a first conductive layer. The first though hole is extended from a second surface to a first surface to expose a conductive pad, and the conductive structure is on the second surface and extended to the first though hole to contact the conductive pad. The conductive structure includes a second conductive layer and a laser stopper. The first isolation layer is on the second surface and covering the conductive structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stopper, and the first conductive layer is on the third surface and extended to the second though hole to contact the laser stopper.

    Abstract translation: 一种芯片封装，包括芯片，第一通孔，导电结构，第一隔离层，第二通孔和第一导电层。 第一通孔从第二表面延伸到第一表面以暴露导电焊盘，并且导电结构在第二表面上并延伸到第一通孔以接触导电焊盘。 导电结构包括第二导电层和激光器塞。 第一隔离层位于第二表面上并覆盖导电结构，第一隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第二表面以暴露激光阻挡件，并且第一导电层在第三表面上并延伸到第二通孔以接触激光器塞。

    CHIP PACKAGE AND FABRICATION METHOD THEREOF
    189.
    发明申请
    CHIP PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
    芯片包装及其制造方法

    公开(公告)号：US20160171273A1

    公开(公告)日：2016-06-16

    申请号：US14967153

    申请日：2015-12-11

    Applicant: XINTEC INC.

    Inventor： Yen-Shih HO ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Hsing-Lung SHEN

    IPC: G06K9/00 ,  H01L21/48 ,  H01L23/498

    CPC classification number: G06K9/0002 ,  G06F3/0414 ,  G06K9/00013 ,  H01L2224/141 ,  H01L2224/16225

    Abstract: A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.

    Abstract translation: 芯片封装包括基板，电容感测层和计算芯片。 基板具有与第一表面相对的第一表面和第二表面，并且电容感测层设置在第二表面上方并且具有与第二表面相对的第三表面，电容感测层包括多个电容感测电极 和多根金属线。 电容感测电极位于第二表面上，并且金属线在电容感测电极上。 计算芯片设置在第三表面上方并电连接到电容感测电极。

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