公开(公告)号：US06204453B1

公开(公告)日：2001-03-20

申请号：US09203956

申请日：1998-12-02

Applicant: Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

Inventor： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

IPC: H05K103

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09554 ,  H05K2203/0733

Abstract: A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.

Abstract translation: 形成印刷电路板或电路卡的方法设置有用作夹在一对可光成像的电介质层之间的电力平面的金属层。 光刻图形金属填充的通孔和光成像的电镀通孔位于光图案化材料中，信号电路位于每个介电材料的表面上，并连接到通孔和电镀通孔。 边界可以在板或卡周围，包括从电介质层之一的边缘终止的金属层。 铜箔上设有间隙孔。 可光成像的可固化介电材料的第一和第二层设置在作为可光成像的材料的铜的相对侧上。 图案在可光成象材料的第一层和第二层上显影，以通过通孔显露金属层。 在铜中的间隙孔处，通孔被开发成在两个电介质层中图案化孔。 此后，可光成像材料，通孔和通孔的表面通过镀铜进行金属化。 这优选通过用光致抗蚀剂和利用光刻技术保护电路的其余部分来实现。 然后去除光致抗蚀剂，留下在两侧具有金属化的电路板或卡，其中心的两侧延伸到铜层，通孔连接两个外部电路化的铜层。

公开(公告)号：US06986198B2

公开(公告)日：2006-01-17

申请号：US10744142

申请日：2003-12-22

Applicant: Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

Inventor： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

IPC: H05K3/36

CPC classification number: H05K3/445 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/0052 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/108 ,  H05K3/426 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0919 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0323 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1394 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer termination in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.

Abstract translation: 提供了一种在两个可光成像的电介质层之间形成具有金属功率平面层的印刷电路卡的方法。 通过孔穿过的光刻金属填充通孔位于光图案化材料中，信号电路位于连接到通孔和电镀通孔的每个介电材料的表面上。 边框可以在卡周围，包括从电介质层之一的边缘终止的金属层。 提供带有间隙孔的铜箔。 第一层和第二层可光成像的可固化电介质材料位于铜的相对两侧。 在可光成像材料的第一层和第二层上形成图案以通过通孔显露金属层。 开发了通孔，在两个电介质层中对其进行图案化。 可光成像材料，通孔和通孔的表面通过镀铜进行金属化，优选使用光致抗蚀剂。

公开(公告)号：US06961995B2

公开(公告)日：2005-11-08

申请号：US10251072

申请日：2002-09-19

Applicant: Lisa J. Jimarez ,  Miguel A. Jimarez ,  Voya R. Markovich ,  Cynthia S. Milkovich ,  Charles H. Perry ,  Brenda L. Peterson

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez ,  Voya R. Markovich ,  Cynthia S. Milkovich ,  Charles H. Perry ,  Brenda L. Peterson

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10 ,  B44C1/22 ,  C03C15/00 ,  H05K7/12 ,  C23E1/00

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3457 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/4605 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/015 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/10734 ,  H05K2203/061 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

公开(公告)号：US06757967B2

公开(公告)日：2004-07-06

申请号：US10119134

申请日：2002-04-09

Applicant: Lisa J. Jimarez ,  Miguel A. Jimarez

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez

IPC: H05K330

CPC classification number: H01L23/16 ,  H01L23/36 ,  H01L23/50 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/15311 ,  Y10S269/90 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49993 ,  Y10T29/53265

Abstract: A chip mounting assembly is provided which includes a dielectric substrate having at least one integrated circuit (I/C) chip mounted thereon. An electrically conductive cover plate is in contact with all the chips with an electrically non-conducting thermally conducting adhesive. A stiffener member is provided which is mounted ante substrate and laterally spaced from the integrated circuit chip. At least one electrically conductive ground pad is formed an the substrate. The stiffener member has at least one through opening therein and electrically conductive adhesive extending through each opening and contacting the cover plate and each ground pad. The invention also provides a method of forming such an I/C chip assembly.

Abstract translation: 提供了一种芯片安装组件，其包括具有安装在其上的至少一个集成电路（I / C）芯片的电介质基板。 导电盖板与具有不导电导热粘合剂的所有芯片接触。 提供了一种加强构件，其被安装在前底座上并与集成电路芯片横向隔开。 至少一个导电接地焊盘形​​成为衬底。 加强件在其中具有至少一个通孔，并且导电粘合剂延伸穿过每个开口并接触盖板和每个接地垫。 本发明还提供了一种形成这种I / C芯片组件的方法。

公开(公告)号：US06756680B2

公开(公告)日：2004-06-29

申请号：US09782471

申请日：2001-02-12

Applicant: Miguel A. Jimarez ,  Cynthia S. Milkovich ,  Mark V. Pierson

Inventor： Miguel A. Jimarez ,  Cynthia S. Milkovich ,  Mark V. Pierson

IPC: H01L2348

CPC classification number: H01L24/12 ,  B23K1/0016 ,  B23K2101/42 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81013 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/351 ,  H05K3/0032 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2203/0415 ,  H05K2203/043 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2924/00014

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.

公开(公告)号：US06492600B1

公开(公告)日：2002-12-10

申请号：US09340758

申请日：1999-06-28

Applicant: Miguel A. Jimarez ,  Ross W. Keesler ,  Voya R. Markovich ,  Rajinder S. Rai ,  Cheryl L. Tytran-Palomaki

Inventor： Miguel A. Jimarez ,  Ross W. Keesler ,  Voya R. Markovich ,  Rajinder S. Rai ,  Cheryl L. Tytran-Palomaki

IPC: H05K109

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/3484 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09863 ,  H05K2203/043 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A chip carrier structure and method for forming the same having a receptor pad formed therein. The structure comprises a circuitized substrate having a conductive element on the surface, an External Dielectric Layer mounted on the circuitized substrate with an opening positioned above the conductive element to form a microvia. The walls of the microvia are first treated to enhance copper adhesion and then are electroplated to provide a receptor pad. Finally, a solder paste is deposited within the microvia to create a solder deposit or bump.

Abstract translation: 一种用于形成其中形成有受体垫的芯片载体结构和方法。 该结构包括在表面上具有导电元件的电路化基板，安装在电路化基板上的外部电介质层，其中开口位于导电元件上方以形成微孔。 首先处理微孔的壁以增强铜的粘附性，然后电镀以提供受体垫。 最后，在微孔内沉积焊膏以产生焊料沉积物或凸块。

公开(公告)号：US06407334B1

公开(公告)日：2002-06-18

申请号：US09727271

申请日：2000-11-30

Applicant: Lisa J. Jimarez ,  Miguel A. Jimarez

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez

IPC: H01L2302

CPC classification number: H01L23/16 ,  H01L23/36 ,  H01L23/50 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/15311 ,  Y10S269/90 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49993 ,  Y10T29/53265

Abstract: A chip mounting assembly includes a dielectric substrate having at least one integrated circuit (I/C) chip mounted thereon. An electrically conductive cover plate is in contact with all the chips with an electrically non-conducting thermally conducting adhesive. A stiffener member is provided which is mounted on the substrate and laterally spaced from the integrated circuit chip. At least one electrically conductive ground pad is formed on the substrate. The stiffener has at least one through opening therein and electrically conductive adhesive extending through each opening and contacting the cover plate and each ground pad.

Abstract translation: 芯片安装组件包括具有安装在其上的至少一个集成电路（I / C）芯片的电介质基板。 导电盖板与具有不导电导热粘合剂的所有芯片接触。 提供了一种加强件，其安装在基板上并与集成电路芯片横向间隔开。 在衬底上形成至少一个导电接地焊盘。 加强件在其中具有至少一个通孔，导电粘合剂延伸穿过每个开口并接触盖板和每个接地垫。

公开(公告)号：US07278207B2

公开(公告)日：2007-10-09

申请号：US11182167

申请日：2005-07-15

Applicant: Lisa J. Jimarez ,  Miguel A. Jimarez ,  Voya R. Markovich ,  Cynthia S. Milkovich ,  Charles H. Perry ,  Brenda L. Peterson

Inventor： Lisa J. Jimarez ,  Miguel A. Jimarez ,  Voya R. Markovich ,  Cynthia S. Milkovich ,  Charles H. Perry ,  Brenda L. Peterson

IPC: H01K3/10 ,  H01R12/04 ,  H01L21/00

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/3457 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/4605 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/015 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/10734 ,  H05K2203/061 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

公开(公告)号：US06639302B2

公开(公告)日：2003-10-28

申请号：US10103602

申请日：2002-03-20

Applicant: Krishna Darbha ,  Miguel A. Jimarez ,  Matthew M. Reiss ,  Sanjeev B. Sathe ,  Charles G. Woychik

Inventor： Krishna Darbha ,  Miguel A. Jimarez ,  Matthew M. Reiss ,  Sanjeev B. Sathe ,  Charles G. Woychik

IPC: H01L2906

CPC classification number: H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15151 ,  H01L2924/00012

Abstract: A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.

Abstract translation: 将半导体器件电耦合到被分成多个段的衬底的方法和结构。 或者，半导体器件可以被分成多个段，并且多个段电耦合到单个衬底。

公开(公告)号：US06558981B2

公开(公告)日：2003-05-06

申请号：US09848510

申请日：2001-05-03

Applicant: Miguel A. Jimarez ,  Marybeth Perrino ,  Son K. Tran ,  Tien Y. Wu

Inventor： Miguel A. Jimarez ,  Marybeth Perrino ,  Son K. Tran ,  Tien Y. Wu

IPC: H01L2144

CPC classification number: H01L21/563 ,  H01L23/13 ,  H01L23/3121 ,  H01L2224/73203 ,  H01L2924/3025

Abstract: An encapsulated semiconductor chip module. The chip module has the overlying encapsulant adhered directly and integrally to bare portions of the substrate to which the chip is mounted. This configuration enhances the adhesion and inhibits unintended delamination of the encapsulant from the balance of the module. The module is made by patterning anchor openings into the solder mask. The anchor openings expose corresponding portions of the substrate. It is important to locate the anchor openings over parts of the substrate that do not have circuitry on them, that is, on bare portions, so as to avoid corrosion or contamination of the circuit connections.

Abstract translation: 封装的半导体芯片模块。 芯片模块具有直接并整体地粘附到芯片所安装的基板的裸露部分的上覆密封剂。 这种构造增强了粘附性，并且阻止了封装材料与模块平衡的意外分层。 该模块通过将锚定开口图案图案化成焊接掩模。 锚定开口露出衬底的相应部分。 重要的是将锚定开口定位在其上没有电路的基板的部分上，即在裸露的部分上，以避免腐蚀或电路连接的污染。