Patent search ap:("INTERNATIONAL BUSINESS MACHINES CORPORATION") AND inv:"Christopher D. Muzzy" Page 2

11.

发明授权
Structures and methods for improving solder bump connections in semiconductor devices 有权
Title translation: 用于改善半导体器件中的焊料凸点连接的结构和方法

公开(公告)号：US09087754B2

公开(公告)日：2015-07-21

申请号：US14522664

申请日：2014-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan

IPC: H01L23/492 , H01L23/00

CPC classification number: H01L24/13 , H01L24/03 , H01L24/05 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05011 , H01L2224/05017 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05551 , H01L2224/05555 , H01L2224/05557 , H01L2224/05644 , H01L2224/13006 , H01L2224/13022 , H01L2224/13025 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2924/00013 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01093 , H01L2924/0132 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/0103 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599

Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a via formed in a dielectric layer to expose a contact pad and a capture pad formed in the via and over the dielectric layer. The capture pad has openings over the dielectric layer to form segmented features. The solder bump is deposited on the capture pad and the openings over the dielectric layer.

Abstract translation: 具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。该结构包括在电介质层中形成的通孔，以露出形成在通孔中和电介质层上的接触焊盘和捕获焊盘。捕获垫在电介质层上具有开口以形成分段特征。焊料凸块沉积在捕获垫上并且在介电层上沉积开口。

12.

发明授权
Solder bump connection and method of making 有权
Title translation: 焊接接头和制造方法

公开(公告)号：US08994173B2

公开(公告)日：2015-03-31

申请号：US13927759

申请日：2013-06-26

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter

IPC: H01L21/4763 , H01L23/00

CPC classification number: H01L24/11 , H01L23/293 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03019 , H01L2224/034 , H01L2224/03614 , H01L2224/03616 , H01L2224/03912 , H01L2224/0401 , H01L2224/05007 , H01L2224/05016 , H01L2224/05027 , H01L2224/05094 , H01L2224/05096 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05568 , H01L2224/05666 , H01L2224/11019 , H01L2224/1134 , H01L2224/114 , H01L2224/1147 , H01L2224/13006 , H01L2224/1308 , H01L2224/131 , H01L2924/00014 , H01L2924/013 , H01L2924/01074 , H01L2924/00012 , H01L2924/04941 , H01L2924/04953 , H01L2924/014

Abstract: A layer of material can protect a surface of a passivation layer against damage during a final via plug process. The protective layer can be a conductive bump limiting metallurgy (BLM) base layer and can include titanium tungsten (TiW), though other materials can be employed. Examples include applying the protective layer after formation of a via opening and prior to formation of a via opening, and can include applying more protective material after conductor plug formation to enhance protection. Photosensitive and non-photosensitive passivation layers can be so protected.

Abstract translation: 一层材料可以保护钝化层的表面，防止在最终的通孔过程中损坏。保护层可以是导电凸块限制冶金（BLM）基层，并且可以包括钛钨（TiW），尽管可以使用其它材料。实例包括在形成通孔开口之后并且在形成通孔开口之前施加保护层，并且可以包括在导体塞形成之后施加更多的保护材料以增强保护。感光和非感光钝化层可以这样保护。

13.

发明申请
PLUG VIA FORMATION BY PATTERNED PLATING AND POLISHING 有权
Title translation: 通过绘图和抛光形成的插件

公开(公告)号：US20150076688A1

公开(公告)日：2015-03-19

申请号：US14026158

申请日：2013-09-13

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck , Jeffrey P. Gambino , Ekta Misra , Christopher D. Muzzy , Wolfgang Sauter

IPC: H01L23/00

CPC classification number: H01L24/81 , H01L23/3171 , H01L23/481 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/036 , H01L2224/03602 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05023 , H01L2224/05026 , H01L2224/0508 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05568 , H01L2224/0558 , H01L2224/05655 , H01L2224/1134 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13025 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/81815 , H01L2924/014 , H01L2924/00014 , H01L2924/01027 , H01L2924/01026 , H01L2924/00012 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953

Abstract: Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.

Abstract translation: 焊接凸块连接和制造焊料凸点连接的方法。在电介质层上形成钝化层。通孔开口从钝化层的顶表面延伸穿过钝化层到介电层中的金属线。钝化层的顶表面上的掩模包括与通孔开口对准的掩模开口。导电层选择性地形成在通路孔和掩模开口中。导电层突出在钝化层的顶表面之上。该方法还包括平坦化钝化层和导电层以限定与金属线耦合的通孔孔中的插塞。

14.

发明申请
CHIP CONNECTION STRUCTURE AND METHOD OF FORMING 审中-公开
Title translation: 芯片连接结构及其形成方法

公开(公告)号：US20150037971A1

公开(公告)日：2015-02-05

申请号：US14510426

申请日：2014-10-09

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang W. Sauter , Timothy D. Sullivan

IPC: H01L23/00

CPC classification number: H01L24/11 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03452 , H01L2224/0346 , H01L2224/0348 , H01L2224/03912 , H01L2224/0401 , H01L2224/05026 , H01L2224/05147 , H01L2224/05571 , H01L2224/05572 , H01L2224/056 , H01L2224/11 , H01L2224/11005 , H01L2224/11452 , H01L2224/1146 , H01L2224/11472 , H01L2224/11903 , H01L2224/11906 , H01L2224/13 , H01L2224/13006 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13147 , H01L2224/16238 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/12042 , H01L2924/00012 , H01L2224/05552 , H01L2924/00

Abstract: Chip connection structures and related methods of forming such structures are disclosed. In one case, an interconnect structure is disclosed, the structure including: a pillar connecting an integrated circuit chip and a substrate, the pillar including a barrier layer, a first copper layer over the barrier layer, and a first solder layer over the first copper layer.

Abstract translation: 公开了形成这种结构的芯片连接结构和相关方法。在一种情况下，公开了一种互连结构，该结构包括：连接集成电路芯片和基板的柱，所述柱包括阻挡层，在阻挡层上的第一铜层，以及在第一铜上的第一焊料层层。

15.

发明授权
Far back end of the line metallization method and structures 有权
Title translation: 线后端的金属化方法和结构

公开(公告)号：US08937009B2

公开(公告)日：2015-01-20

申请号：US13870026

申请日：2013-04-25

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck , Jeffrey P. Gambino , Karen P. McLaughlin , Ekta Misra , Christopher D. Muzzy , Eric D. Perfecto , Wolfgang Sauter

IPC: H01L21/768 , H01L21/44 , H01L23/498 , H01L23/00

CPC classification number: H01L24/11 , H01L22/34 , H01L23/3192 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/03462 , H01L2224/03622 , H01L2224/03914 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05558 , H01L2224/05568 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/06135 , H01L2224/06136 , H01L2224/11462 , H01L2224/11622 , H01L2224/11849 , H01L2224/11914 , H01L2224/13023 , H01L2224/13026 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13147 , H01L2224/94 , H01L2924/00014 , H01L2924/1305 , H01L2924/01047 , H01L2924/01074 , H01L2224/11 , H01L2224/03 , H01L2924/00 , H01L2224/05552

Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon. The mask layer is removed, an additional mask layer is formed and patterned with third opening(s) exposing only the under-bump pad(s) and solder material is deposited on the under-bump pad(s).

Abstract translation: 公开了半导体晶片处理期间的金属化方法和所得到的结构。在该方法中，钝化层被图案化，其中第一开口在上方对齐并垂直延伸到下面的金属结构。形成掩模层并用第一开口对准的第二开口进行图案化，从而形成垂直延伸穿过掩模层和钝化层到下面的金属结构的两层开口。电沉积工艺在双层开口中形成凸点下焊盘和附加的金属部件，其不同于凸块下焊盘（例如，引线焊盘;最终垂直的）裂缝结构部分和/或探针垫）。每个凸点下焊盘和附加的金属特征最初包括铜上的金属盖层。去除掩模层，形成另外的掩模层并用仅暴露凸块下焊盘的第三开口图案化，并且焊料材料沉积在凸块下焊盘上。

16.

发明申请
SEMICONDUCTOR TEST WAFER AND METHODS FOR USE THEREOF 有权
Title translation: 半导体测试波形及其使用方法

公开(公告)号：US20140266292A1

公开(公告)日：2014-09-18

申请号：US13835358

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter

IPC: G01R31/26

CPC classification number: H01L22/34

Abstract: A test wafer is disclosed with a first side configured to have integrated circuits formed thereon and a second side with a test structure formed thereon. The test wafer can include electrical test structures embedded in the second side of the wafer. An electrical test of the test wafer can be performed after handling by a tool used in a wafer manufacturing process to determine if the tool caused a defect on the second side of the wafer. The test structure can include a blanket layer disposed on the second side of the wafer. The test wafer can then be exposed to a wet etch and inspected thereafter for the presence of an ingress path caused from the etch chemistry. The presence of an ingress path is an indication that the tool used prior to the wet etch caused a defect in the wafer.

Abstract translation: 公开了一种测试晶片，其第一侧被配置为具有形成在其上的集成电路，以及形成有测试结构的第二侧。测试晶片可以包括嵌入晶片第二侧的电测试结构。测试晶片的电气测试可以在通过晶片制造过程中使用的工具处理之后进行，以确定工具是否在晶片的第二侧引起缺陷。测试结构可以包括布置在晶片的第二侧上的覆盖层。然后可以将测试晶片暴露于湿蚀刻，然后检查是否存在由蚀刻化学物质引起的入口路径。进入路径的存在表示在湿蚀刻之前使用的工具导致晶片中的缺陷。

17.

发明申请
OVERCOMING CHIP WARPING TO ENHANCE WETTING OF SOLDER BUMPS AND FLIP CHIP ATTACHES IN A FLIP CHIP PACKAGE 有权
Title translation: 覆盖芯片保证加强焊接芯片和飞溅芯片附件在卷芯片包装中的磨损

公开(公告)号：US20140084453A1

公开(公告)日：2014-03-27

申请号：US13626032

申请日：2012-09-25

Applicant: International Business Machines Corporation

Inventor： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Nathalie Normand , David L. Questad , Wolfgang Sauter , Timothy D. Sullivan

IPC: H01L23/48 , H01L21/60

CPC classification number: H01L23/3164 , H01L23/291 , H01L23/293 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/11001 , H01L2224/11011 , H01L2224/1131 , H01L2224/11849 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2224/81007 , H01L2224/81191 , H01L2924/12042 , H01L2924/15174 , H01L2924/15311 , H01L2924/3511 , H01L2924/00014 , H01L2924/00012 , H01L2924/01047 , H01L2924/00

Abstract: Structures and methods for forming good electrical connections between an integrated circuit (IC) chip and a chip carrier of a flip chip package include forming one of: a tensile layer on a front side of the IC chip, which faces a tops surface of the chip carrier, and a compressive layer on the backside of the IC chip. Addition of one of: a tensile layer to the front side of the IC chip and a compressive layer the backside of the IC chip, may reduce or modulate warpage of the IC chip and enhance wetting of opposing solder surfaces of solder bumps on the IC chip and solder formed on flip chip (FC) attaches of a chip carrier during making of the flip chip package.

Abstract translation: 用于在集成电路（IC）芯片和倒装芯片封装的芯片载体之间形成良好电连接的结构和方法包括形成以下之一：IC芯片正面上的面向芯片顶表面的拉伸层载体和IC芯片背面的压缩层。添加IC芯片的前侧的拉伸层和IC芯片的背面的压缩层可以减少或调制IC芯片的翘曲并增强IC芯片上的焊料凸块的相对焊接表面的润湿并且在制造倒装芯片封装期间在芯片载体的倒装芯片（FC）上形成焊料。