公开(公告)号：US20160211233A1

公开(公告)日：2016-07-21

申请号：US14994537

申请日：2016-01-13

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/02 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00015 ,  H01L2924/0549 ,  H01L2924/10156 ,  H01L2924/15153 ,  H01L2924/3511 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/0781 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0544 ,  H01L2924/0542 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/0231 ,  H01L2224/48

Abstract: A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.

Abstract translation: 提供了一个芯片模块。 芯片模块包括具有上表面，下表面和侧壁的芯片。 芯片包括与上表面相邻的信号焊盘区域。 凹部沿着芯片的侧壁从上表面向下表面延伸。 再分配层电连接到信号焊盘区域并延伸到凹部中。 电路板位于上表面和下表面之间并延伸到凹槽中。 导电结构位于凹部中并将电路板电连接到再分布层。 还提供了一种用于形成芯片模块的方法。

公开(公告)号：US20160204061A1

公开(公告)日：2016-07-14

申请号：US14992776

申请日：2016-01-11

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE

IPC: H01L23/522 ,  H01L21/304 ,  H01L21/268 ,  H01L21/76 ,  H01L21/78 ,  H01L21/683 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  G06K9/0002 ,  H01L21/268 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5283 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package including a chip, a first though hole, a conductive structure, a first isolation layer, a second though hole and a first conductive layer. The first though hole is extended from a second surface to a first surface to expose a conductive pad, and the conductive structure is on the second surface and extended to the first though hole to contact the conductive pad. The conductive structure includes a second conductive layer and a laser stopper. The first isolation layer is on the second surface and covering the conductive structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stopper, and the first conductive layer is on the third surface and extended to the second though hole to contact the laser stopper.

Abstract translation: 一种芯片封装，包括芯片，第一通孔，导电结构，第一隔离层，第二通孔和第一导电层。 第一通孔从第二表面延伸到第一表面以暴露导电焊盘，并且导电结构在第二表面上并延伸到第一通孔以接触导电焊盘。 导电结构包括第二导电层和激光器塞。 第一隔离层位于第二表面上并覆盖导电结构，第一隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第二表面以暴露激光阻挡件，并且第一导电层在第三表面上并延伸到第二通孔以接触激光器塞。

公开(公告)号：US20170047455A1

公开(公告)日：2017-02-16

申请号：US15231590

申请日：2016-08-08

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Tsang-Yu LIU

IPC: H01L31/0216 ,  H01L31/18 ,  H01L33/00 ,  H01L33/46 ,  H01L33/52

CPC classification number: H01L33/005 ,  G01S7/4813 ,  G01S17/026 ,  H01L31/173 ,  H01L33/46 ,  H01L33/52 ,  H01L2224/11

Abstract: This present invention provides a novel sensing chip package and a manufacturing method thereof, and in particular provides a proximity sensing chip package and a manufacturing thereof, which is characterized by forming a light blocking layer surrounding the light emitting device of the sensor to block the lateral light emitted by the light emitting device to reduce the interference of the lateral light and enhance the sensitivity of the light sensing device.

Abstract translation: 本发明提供了一种新颖的感测芯片封装及其制造方法，并且特别地提供了一种接近感测芯片封装及其制造方法，其特征在于形成围绕传感器的发光器件的遮光层以阻挡侧面 由发光器件发射的光以减少横向光的干扰并增强光感测装置的灵敏度。

公开(公告)号：US20160372445A1

公开(公告)日：2016-12-22

申请号：US15164660

申请日：2016-05-25

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/492 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/065 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/3128 ,  H01L23/492 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L27/14618 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/16235

Abstract: A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括其中具有导电焊盘并且与其第一表面相邻的衬底。 芯片附着在与基板的第一表面相对的第二表面上，并且封装层覆盖芯片。 第一再分配层设置在衬底的第二表面和封装层之间，第二再分布层设置在封装层上。 第一导电结构和第二导电结构设置在封装层中。 第一和第二导电结构中的每一个分别包括至少一个结合球。 第一导电结构被配置为连接第一和第二再分配层，并且第二导电结构被配置为连接第二再分布层和芯片。 还提供了一种形成芯片封装的方法。

公开(公告)号：US20160133588A1

公开(公告)日：2016-05-12

申请号：US14931633

申请日：2015-11-03

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L21/311 ,  H01L21/78 ,  H01L21/02 ,  H01L21/683 ,  H01L21/31

CPC classification number: H01L24/09 ,  G06F21/32 ,  H01L21/02013 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/08235 ,  H01L2224/08237 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad in the first though hole. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface, and has a second though hole to expose the laser stopper. The redistribution layer is located on the third surface, a sidewall of the second though hole, and the laser stopper in the second though hole. The conductive structure is located on the redistribution.

Abstract translation: 芯片封装包括芯片，激光器停止器，隔离层，再分布层，绝缘层和导电结构。 芯片具有导电焊盘，第一表面和第二表面。 导电垫位于第一表面上。 第二表面具有第一通孔以暴露导电垫。 激光停止器位于第一通孔中的导电垫上。 隔离层位于第二表面和第一通孔中。 隔离层具有与第二表面相对的第三表面，并且具有第二通孔以暴露激光制动器。 再分配层位于第三表面，第二通孔的侧壁和第二通孔中的激光停止件。 导电结构位于再分配上。

公开(公告)号：US20150325557A1

公开(公告)日：2015-11-12

申请号：US14709216

申请日：2015-05-11

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L25/16 ,  H01L23/00 ,  H01L27/146 ,  H01L25/00 ,  H01L21/56 ,  H01L23/522 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/17 ,  H01L24/20 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14634 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48465 ,  H01L2224/73209 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/146 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00

Abstract: A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.

Abstract translation: 提供了包括第一基板的芯片封装。 第一基板包括感测装置。 第二基板附着在第一基板上并且包括集成电路装置。 第一导电结构通过设置在第一基板上的再分配层电连接到感测装置和集成电路装置。 绝缘层覆盖第一基板，第二基板和再分布层。 绝缘层在其中具有孔，并且第二导电结构设置在孔的底部下方。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20150255358A1

公开(公告)日：2015-09-10

申请号：US14638219

申请日：2015-03-04

Applicant: XINTEC INC.

Inventor： Ying-Nan WEN ,  Chien-Hung LIU ,  Ho-Yin YIU

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/3114 ,  H01L21/268 ,  H01L21/31053 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/034 ,  H01L2224/0362 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/12042 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The semiconductor chip has an electronic component and a conductive pad that are electrically connected and disposed on an upper surface of the semiconductor chip. The first depression and first redistribution layer extend from the upper surface toward the lower surface of the semiconductor chip. The first redistribution layer and the conductive pad are electrically connected. The second depression and the second redistribution layer extends from the lower surface toward the upper surface and is in connection with the first depression through a connection portion. The second redistribution layer is electrically connected to the first redistribution layer through the connection portion. The packaging layer is disposed on the lower surface.

Abstract translation: 半导体封装包括半导体芯片，第一和第二凹陷，第一和第二再分布层和封装层。 半导体芯片具有电连接并设置在半导体芯片的上表面上的电子部件和导电焊盘。 第一凹陷部和第一再分布层从半导体芯片的上表面向下表面延伸。 第一再分配层和导电焊盘电连接。 第二凹陷和第二再分布层从下表面向上表面延伸并且通过连接部分与第一凹陷连接。 第二再分配层通过连接部分电连接到第一再分配层。 包装层设置在下表面上。

公开(公告)号：US20140332908A1

公开(公告)日：2014-11-13

申请号：US14339360

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chao-Yen LIN ,  Wei-Luen SUEN ,  Chien-Hui CHEN ,  Ho-Yin YIU

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/76802 ,  G06K9/00053 ,  H01L21/561 ,  H01L21/76877 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.

Abstract translation: 提供了包括芯片的芯片封装。 芯片包括与芯片的上表面相邻的感测区域或器件区域。 感测阵列位于感测区域或设备区域中并且包括多个感测单元。 多个第一开口位于芯片中并且相应地暴露感测单元。 多个导电延伸部分设置在第一开口中并且电连接到感测单元，其中导电延伸部分从第一开口延伸到芯片的上表面上。 还提供了一种用于形成芯片封装的方法。