公开(公告)号：US20180019137A1

公开(公告)日：2018-01-18

申请号：US15545758

申请日：2016-03-18

申请人： Atotech Deutschland GmbH

发明人： Christof SUCHENTRUNK ,  Christian SCHWARZ

IPC分类号： H01L21/3205 ,  C23C18/36 ,  C23C18/38 ,  C23C18/16 ,  H01L21/768 ,  H01L21/288

CPC分类号： H01L21/32053 ,  C23C18/1642 ,  C23C18/1655 ,  C23C18/1678 ,  C23C18/1692 ,  C23C18/1879 ,  C23C18/34 ,  C23C18/36 ,  C23C18/38 ,  H01L21/288 ,  H01L21/76838

摘要： The present invention relates to an activation composition for activation of silicon substrates, which is an aqueous solution comprising a source of palladium ions, a source of fluoride ions and at least two aromatic acids. The present invention further relates to a method for its use and optionally for subsequent metallization of such treated substrates. The method can be employed in semiconductor and solar cell manufacturing.

公开(公告)号：US20170323966A1

公开(公告)日：2017-11-09

申请号：US15656290

申请日：2017-07-21

申请人： Intel Corporation

发明人： Sameer S. Pradhan ,  Subhash M. Joshi ,  Jin-Sung Chun

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417 ,  H01L29/16 ,  H01L23/48 ,  H01L21/3205 ,  H01L21/283

CPC分类号： H01L29/785 ,  H01L21/02 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/48 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

公开(公告)号：US09698211B2

公开(公告)日：2017-07-04

申请号：US15148004

申请日：2016-05-06

申请人： Texas Instruments Incorporated

发明人： Rajni J. Aggarwal ,  Jau-Yuann Yang

IPC分类号： H01L21/28 ,  H01L49/02 ,  H01L27/06 ,  H01L27/092 ,  H01L21/266 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L28/20 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/283 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/4916 ,  H01L29/66583 ,  H01L29/6659

摘要： An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

公开(公告)号：US09679808B2

公开(公告)日：2017-06-13

申请号：US14988374

申请日：2016-01-05

申请人： ASM International N.V.

发明人： Suvi P. Haukka ,  Antti Niskanen ,  Marko Tuominen

IPC分类号： H01L21/4763 ,  H01L21/768 ,  C23C16/02 ,  C23C16/14 ,  C23C16/455 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3205

CPC分类号： H01L21/7685 ,  C23C16/0227 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/02068 ,  H01L21/02697 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76883

摘要： Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In preferred embodiments, a first precursor forms a layer or adsorbed species on the first surface and is subsequently reacted or converted to form a metallic layer. Preferably the deposition temperature is selected such that a selectivity of above about 90% is achieved.

公开(公告)号：US20170125418A1

公开(公告)日：2017-05-04

申请号：US15407598

申请日：2017-01-17

申请人： Samsung Electronics Co., Ltd.

发明人： JAEYOUNG PARK ,  SUNGHO KANG ,  KICHUL KIM ,  Sunyoung LEE ,  HAN KI LEE ,  BONYOUNG KOO

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L29/34 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/0206 ,  H01L21/302 ,  H01L21/306 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

摘要： A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700° C.

公开(公告)号：US09640539B2

公开(公告)日：2017-05-02

申请号：US14970707

申请日：2015-12-16

申请人： Texas Instruments Incorporated

发明人： Steven Alan Lytle

IPC分类号： H01L27/118 ,  H01L27/11 ,  H01L21/768 ,  H01L21/283 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L23/485 ,  H01L27/02 ,  H01L23/522 ,  H01L23/535

CPC分类号： H01L27/1104 ,  H01L21/283 ,  H01L21/32053 ,  H01L21/76831 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/8238 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1116 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.

公开(公告)号：US20170103918A1

公开(公告)日：2017-04-13

申请号：US15384446

申请日：2016-12-20

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Audrey Hsiao-Chiu Hsu ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Hsien-Cheng Wang ,  Shih-Wen Liu ,  Hsin-Ying Lin

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/535

CPC分类号： H01L21/76897 ,  H01L21/2633 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/32105 ,  H01L21/3212 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/088 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.

公开(公告)号：US09613972B1

公开(公告)日：2017-04-04

申请号：US15080700

申请日：2016-03-25

申请人： SK hynix Inc.

发明人： Jong Hoon Kim

IPC分类号： H01L27/146 ,  H01L27/11524 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3105

CPC分类号： H01L21/31053 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/764 ,  H01L27/11531

摘要： In an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include forming a pattern group on a substrate, the substrate being divided into first and second regions, each pattern including a silicon layer, forming an insulating pattern on the substrate, the insulating pattern partially exposing the silicon layer on the first region and blocking the silicon layer on the second region, converting the exposed silicon layer on the first region to a silicide layer while the blocked silicon layer on the second region is protected from the conversion, and performing a subsequent process using, as an overlay vernier, at least a portion of the pattern group formed on the second region.

公开(公告)号：US09601606B2

公开(公告)日：2017-03-21

申请号：US14990941

申请日：2016-01-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Alan B. Botula ,  Max L. Lifson ,  James A. Slinkman ,  Theodore G. Van Kessel ,  Randy L. Wolf

IPC分类号： H01L29/08 ,  H01L29/732 ,  H01L23/367 ,  H01L23/373 ,  H01L29/78 ,  H01L29/45 ,  H01L23/525 ,  H01L21/02 ,  H01L21/285 ,  H01L21/762 ,  H01L49/02 ,  H01L29/06 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/41 ,  H01L21/48 ,  H01L23/48 ,  H01L23/485

CPC分类号： H01L23/3677 ,  B82Y10/00 ,  H01L21/02112 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02271 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02603 ,  H01L21/02628 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/4882 ,  H01L21/7624 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5256 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/413 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/732 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

公开(公告)号：US09593422B2

公开(公告)日：2017-03-14

申请号：US14667691

申请日：2015-03-25

申请人： HITACHI KOKUSAI ELECTRIC INC.

发明人： Masayuki Asai ,  Koichi Honda ,  Mamoru Umemoto ,  Kazuyuki Okuda

IPC分类号： C23C16/455 ,  C23C16/08 ,  H01J37/32 ,  H01L21/02 ,  C23C16/52 ,  C23C16/34 ,  C23C16/40 ,  C23C16/44 ,  C23C16/509 ,  C23C16/54 ,  H01L21/033 ,  H01L21/3205

CPC分类号： C23C16/52 ,  C23C16/08 ,  C23C16/345 ,  C23C16/401 ,  C23C16/4401 ,  C23C16/4408 ,  C23C16/45542 ,  C23C16/45544 ,  C23C16/509 ,  C23C16/54 ,  H01J37/3244 ,  H01J37/32899 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/0337 ,  H01L21/32051 ,  H01L21/32053

摘要： Disclosed is a method of manufacturing a semiconductor device including: performing a pre-process to a substrate, on a surface of which a metal film or a GST film is formed, such that a first film is formed on the metal film or the GST film by executing at least one cycle of alternately performing (i) supplying a first processing gas, and (ii) supplying a second processing gas that is not activated by plasma excitation; and performing a formation process to the substrate to which the pre-process has been performed such that a second film is formed on the first film by executing at least one cycle of alternately (i) supplying the first processing gas, and (ii) supplying the second processing gas that is activated by plasma excitation.

摘要翻译： 公开了一种制造半导体器件的方法，包括：在其表面上形成金属膜或GST膜的基板上进行预处理，使得在金属膜或GST膜上形成第一膜 通过执行交替执行（i）供应第一处理气体的至少一个循环，和（ii）提供未被等离子体激发而激活的第二处理气体; 并且对已经进行了预处理的基板进行形成处理，使得通过执行交替地（i）供应第一处理气体的至少一个循环，并且（ii）提供第一膜，形成第二膜，从而在第一膜上形成第二膜 通过等离子体激发而激活的第二处理气体。