公开(公告)号：US20120138338A1

公开(公告)日：2012-06-07

申请号：US13365755

申请日：2012-02-03

Applicant: Han KIM ,  Hyung-Sik Choi ,  Dae-Hyun Park

Inventor： Han KIM ,  Hyung-Sik Choi ,  Dae-Hyun Park

IPC: H05K1/00

CPC classification number: H05K1/0236 ,  H05K1/0237 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/09736 ,  H05K2201/09745

Abstract: A printed circuit board having stepped conduction layer includes at least one conduction layer configured for use as a signal transmission layer, the at least one conduction layer being divided into at least two base regions and at least one connecting region connecting any adjacent two of the base regions, and the connecting region being stepped to a lower height than those of the base regions. A lower surface of the connecting region lies on a same plane as a lower surface of the base region, or an upper surface of the connecting region lies on a same plane as an upper surface of the base region. A bridge connecting structure between the connecting regions and the base regions is disposed in possible noise transfer paths between a noise source and a noise attenuation target positioned on the printed circuit board.

Abstract translation: 具有阶梯式导电层的印刷电路板包括被配置为用作信号传输层的至少一个导电层，所述至少一个导电层被分成至少两个基极区域和至少一个连接区域， 区域，并且连接区域被阶梯到比基部区域低的高度。 连接区域的下表面位于与基底区域的下表面相同的平面上，或者连接区域的上表面位于与基底区域的上表面相同的平面上。 在连接区域和基极区域之间的桥连接结构设置在位于印刷电路板上的噪声源和噪声衰减目标之间的可能的噪声传递路径中。

公开(公告)号：US08193556B2

公开(公告)日：2012-06-05

申请号：US12714413

申请日：2010-02-26

Applicant: Charles W. C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

Inventor： Charles W. C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

IPC: H01L33/00 ,  H01L23/34

CPC classification number: H01L21/486 ,  H01L21/4882 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L33/483 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/32188 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15153 ,  H01L2924/16152 ,  H01L2924/19041 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/182 ,  H05K3/0061 ,  H05K2201/09054 ,  H05K2201/09745 ,  H05K2201/10106 ,  H01L2224/05599

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post and a base. The semiconductor device extends into a cavity in the post, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, and the base extends laterally from the post. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace is located outside the cavity and provides signal routing between a pad and a terminal.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线和粘合剂。 散热器包括一个柱子和一个底座。 半导体器件延伸到柱中的空腔中，电连接到导电迹线并且热连接到散热器。 柱从基部向上延伸到粘合剂中的开口中，并且基部从柱横向延伸。 粘合剂在柱和导电迹线之间以及基部和导电迹线之间延伸。 导电迹线位于腔体外部，并提供焊盘和端子之间的信号路由。

公开(公告)号：US20120111728A1

公开(公告)日：2012-05-10

申请号：US13283329

申请日：2011-10-27

Applicant: Suk Hyeon Cho ,  Myeong Ho Hong

Inventor： Suk Hyeon Cho ,  Myeong Ho Hong

IPC: C25D1/00

CPC classification number: H05K3/4007 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K3/205 ,  H05K2201/09745 ,  H05K2203/0338 ,  H01L2924/00

Abstract: Disclosed herein is a method of manufacturing a circuit board. The method of manufacturing a circuit board according to a preferred embodiment of the present invention is configured to include (A) forming a cavity 115 for a bump on one surface 111 of a carrier 110, (B) forming a bump 130 in the cavity 115 for the bump through an electroplating process, (C) laminating an insulating layer 140 on one surface 111 of the carrier 110 so as to apply the bump 130, (D) forming a circuit layer 150 including a via 155 connected with the bump 130 on the insulating layer 140, and (E) removing the carrier 110, whereby the process of forming separate solder balls is removed by forming the cavities 111 for the bumps in the carriers 110 to form the bumps, thereby simplifying the process of manufacturing a circuit board and reducing the lead time.

Abstract translation: 这里公开了一种制造电路板的方法。 根据本发明的优选实施例的制造电路板的方法被配置为包括（A）在载体110的一个表面111上形成用于凸块的空腔115，（B）在空腔115中形成凸块130 对于通过电镀工艺的凸块，（C）在载体110的一个表面111上层叠绝缘层140以施加凸起130，（D）形成包括与凸起130连接的通孔155的电路层150 绝缘层140和（E）去除载体110，由此通过形成用于载体110中的凸点的空腔111来形成分离的焊球的过程以形成凸起，从而简化了制造电路板的过程 并缩短交货时间。

公开(公告)号：US20120103680A1

公开(公告)日：2012-05-03

申请号：US13348708

申请日：2012-01-12

Applicant: Seiji SHIRAI ,  Kenichi SHIMADA ,  Motoo ASAI

Inventor： Seiji SHIRAI ,  Kenichi SHIMADA ,  Motoo ASAI

IPC: H05K1/11

CPC classification number: H05K3/4661 ,  H05K3/108 ,  H05K3/381 ,  H05K3/382 ,  H05K3/421 ,  H05K3/423 ,  H05K2201/0129 ,  H05K2201/015 ,  H05K2201/0278 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09745 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24917 ,  Y10T428/31681

Abstract: A multilayer printed wiring board includes a multilayered structure having conductor circuit layers and interlaminar insulative layers, the interlaminar insulative layers including an outermost interlaminar insulative layer, the conductor circuit layers including an outermost conductor circuit layer formed over the outermost interlaminar insulative, a filled-viahole formed in the outermost interlaminar insulative layer and having one or more metal plating fillings and completely closing a hole formed through the outermost interlaminar insulative layer such that the metal plating of the filled-viahole extends out of the hole and forms a substantially flat surface, and solder bumps including a first solder bump formed on the substantially flat surface of the filled-viahole and a second solder bump formed on a surface portion in the outermost conductor circuit layer. The substantially flat surface of the filled-viahole is leveled substantially at the same height as the surface portion of the outermost conductor circuit layer.

Abstract translation: 多层印刷线路板包括具有导体电路层和层间绝缘层的多层结构，所述层间绝缘层包括最外层间绝缘层，所述导体电路层包括形成在最外层间绝缘体上的最外导体电路层，填充通孔 形成在最外层间绝缘层中并且具有一个或多个金属电镀填充物并且完全闭合通过最外层间绝缘层形成的孔，使得填充通孔的金属镀层延伸出孔并形成基本平坦的表面，并且 焊料凸点包括形成在填充通孔的基本上平坦的表面上的第一焊料凸块和形成在最外导体电路层的表面部分上的第二焊料凸点。 填充通孔的基本上平坦的表面基本上与最外面的导体电路层的表面部分的高度平齐。

公开(公告)号：US08157412B2

公开(公告)日：2012-04-17

申请号：US12591765

申请日：2009-12-01

Applicant: Shun-Tian Lin ,  Chao-Tung Chung

Inventor： Shun-Tian Lin ,  Chao-Tung Chung

IPC: F21V7/00 ,  F21V9/16 ,  F21V13/10

CPC classification number: H05K1/021 ,  F21K9/00 ,  H01L25/0753 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H05K2201/09745 ,  H05K2201/10106 ,  H05K2201/2054 ,  Y10S362/80 ,  Y10T29/4935 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light emitting diode substrate assembly has a metal substrate, a circuit board, multiple chip strings, an annular wall and an encapsulant. The circuit board is mounted on the top surface of the substrate and has multiple through holes and multiple current conducting lines. The chip strings are mounted on the substrate and respectively in the through hole in the circuit board. Each chip string has at least one light emitting diode chip connected electrically to two corresponding current conducting lines on the circuit board with bonding wires. Accordingly, the heat generating during the operation of the chips can be efficiently dissipated from the substrate.

Abstract translation: 发光二极管基板组件具有金属基板，电路板，多个芯片串，环形壁和密封剂。 电路板安装在基板的顶表面上，并具有多个通孔和多条电流导线。 芯片串安装在基板上，分别安装在电路板的通孔中。 每个芯片串具有至少一个发光二极管芯片，其电连接到具有接合线的电路板上的两个对应的电流导线。 因此，能够有效地从基板散失芯片运转时的发热。

公开(公告)号：US20120024575A1

公开(公告)日：2012-02-02

申请号：US13202209

申请日：2009-02-20

Applicant: Guangjun Zhang ,  Yuanchun Xie

Inventor： Guangjun Zhang ,  Yuanchun Xie

IPC: H05K7/20 ,  H05K3/30

CPC classification number: H01L23/3677 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0243 ,  H05K1/182 ,  H05K3/0061 ,  H05K3/429 ,  H05K2201/0959 ,  H05K2201/09745 ,  H05K2201/10166 ,  H05K2201/10416 ,  Y10T29/4913 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A thermal pad (602, 612, 622, 702, 712) formed on a Printed Circuit Board and a method (900) of formed the thermal pad (602, 612, 622, 702, 712) are provided. The thermal pad (602, 612, 622, 702, 712) comprises in its interior one or more coins (604, 614, 624, 704, 714) has a height equal to a thickness of the PCB, and is made of metal or alloy, inserted into a corresponding one of one or more plated cutouts straight through the PCB in the thermal pad, and bonded to side walls of the corresponding one of the one or more plated cutouts with a paste capable of resisting a temperature of 250° C. or above. The plurality of through via (606, 616, 626, 706, 716) are plated, and lugged with a solder mask. The thermal pad (602, 612, 622, 702, 712) has a flat top surface and a flat bottom surface, either of which is coplanar with a corresponding one of top and bottom surfaces of the PCB. A PCB having formed thereon the above thermal pad (602, 612, 622, 702, 712) is also provided.

Abstract translation: 形成在印刷电路板上的散热垫（602,612,622,702,712）和形成热垫（602,612,622,702,712）的方法（900）。 散热垫（602,612,622,702,712）在其内部包括一个或多个硬币（604,614,624,704,714）的高度等于PCB的厚度，并且由金属或 合金，将一个或多个电镀切口中相应的一个插入到热垫中的PCB上，并且用能够耐受250℃温度的粘合剂粘合到一个或多个电镀切口中相应的一个的侧壁上 或以上。 多个通孔（606,616,626,706,716）被电镀，并且用焊接掩模拉出。 热垫（602,612,622,702,712）具有平坦的顶表面和平坦的底表面，其中任一个与PCB的顶表面和底表面中的相应一个共面。 还提供了其上形成有上述散热垫（602,612,622,702,712）的PCB。

公开(公告)号：US08106494B2

公开(公告)日：2012-01-31

申请号：US13016341

申请日：2011-01-28

Applicant: Chun Ying Lin ,  Geng Shin Shen ,  Yu Tang Pan ,  Shih Wen Chou

Inventor： Chun Ying Lin ,  Geng Shin Shen ,  Yu Tang Pan ,  Shih Wen Chou

IPC: H01L23/495

CPC classification number: H01L21/4842 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K3/3426 ,  H05K2201/09745 ,  H05K2201/10689 ,  H05K2201/10787 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A leadframe employed by a leadless package comprises a plurality of package units and an adhesive tape. Each of the package units has a die pad with a plurality of openings and a plurality of pins disposed in the plurality of openings. The adhesive tape is adhered to the surfaces of the plurality of package units and fixes the die pad and the plurality of pins.

Abstract translation: 由无引线封装采用的引线框架包括多个封装单元和胶带。 每个封装单元具有带有多个开口的管芯焊盘和设置在多个开口中的多个销。 粘合带粘附到多个封装单元的表面并固定芯片焊盘和多个引脚。

公开(公告)号：US08030579B2

公开(公告)日：2011-10-04

申请号：US12099957

申请日：2008-04-09

Applicant: Yukihiko Toyoda ,  Yoichiro Kawamura ,  Tomoyuki Ikeda

Inventor： Yukihiko Toyoda ,  Yoichiro Kawamura ,  Tomoyuki Ikeda

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/116 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/068 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09745 ,  H01L2924/00

Abstract: An object of the present invention is to provide a multilayered printed circuit board having a short wiring distance of the conductor circuits, wide option of the design of the conductor circuits and additionally excellent in reliability since cracking scarcely takes place in the interlaminar resin insulating layers in the vicinity of via-holes. The present invention is a multilayered printed circuit board comprising: a conductor circuit and an interlaminar resin insulating layer serially formed on a substrate in alternate fashion and in repetition, wherein a connection of the conductor circuits through the interlaminar resin insulating layers is performed by a via-hole, wherein via-holes in different level layers among the via-holes are formed so as to form a stack-via structure, and wherein at least one of the land diameters of the above-mentioned via-holes in different level layers having the stack via structure is different from the land diameters of other via-holes.

Abstract translation: 本发明的目的是提供一种具有导体电路的布线距离短的多层印刷电路板，可广泛选择导体电路的设计，并且由于在层间树脂绝缘层中几乎不发生破裂 通孔附近。 本发明是一种多层印刷电路板，包括：导体电路和层间树脂绝缘层，其以交替的方式和重复地串联形成在基板上，其中通过层间树脂绝缘层的导体电路的连接通过通孔 孔，其中形成通孔中的不同级别的通孔，以形成堆叠通孔结构，并且其中不同层级中的上述通孔的平台直径中的至少一个具有 堆叠通孔结构不同于其它通孔的焊盘直径。

公开(公告)号：US07977805B2

公开(公告)日：2011-07-12

申请号：US11270651

申请日：2005-11-10

Applicant: Toshiharu Seko

Inventor： Toshiharu Seko

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/4985 ,  H01L21/563 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1579 ,  H05K1/111 ,  H05K1/189 ,  H05K3/244 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0369 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flexible wiring substrate is provided which realizes a fine pitch of a wiring pattern and improves mechanical strength of the wiring pattern so as to prevent breaks or exfoliation of the wiring pattern. A flexible wiring substrate 3 of the present invention includes an insulation tape 6, and a wiring pattern 7 formed on the insulation tape 6. A thickness of the wiring pattern 7 is made thinner in a mounting region, where a semiconductor element is connected to, than in a non-mounting region.

Abstract translation: 提供一种柔性布线基板，其实现布线图案的细间距，并且提高布线图案的机械强度，以防止布线图案的断裂或剥离。 本发明的柔性布线基板3包括绝缘带6和形成在绝缘带6上的布线图案7.布线图案7的厚度在半导体元件连接的安装区域中变薄， 比在非安装区域。

公开(公告)号：US20110157897A1

公开(公告)日：2011-06-30

申请号：US12968660

申请日：2010-12-15

Applicant: Tsung-Jen Liao ,  Chung-Kai Wang ,  Yuan-Hsin Liu ,  Yao-Tsung Hsu

Inventor： Tsung-Jen Liao ,  Chung-Kai Wang ,  Yuan-Hsin Liu ,  Yao-Tsung Hsu

IPC: F21V29/00 ,  B23K31/02

CPC classification number: H05K1/021 ,  F21K9/00 ,  F21V29/70 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/62 ,  H01L33/64 ,  H01L2224/48247 ,  H05K2201/09054 ,  H05K2201/09745 ,  H05K2201/10106 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A light emitting diode module includes: a printed circuit board including an upper circuit layer, a lower metal layer, an insulating layer, and a plurality of through holes; a metallic heat sink formed with a plurality of chip-support portions and disposed below the printed circuit board; a thermal connection layer that has lower and upper surfaces respectively bonded to the heat sink and the lower metal layer of the printed circuit board; and a plurality of light emitting diode chips, each of which is placed in contact with and bonded to one of the chip-support portions and each of which is electrically connected to the upper circuit layer. A method for making the light emitting diode module is also disclosed.

Abstract translation: 发光二极管模块包括：印刷电路板，包括上电路层，下金属层，绝缘层和多个通孔; 金属散热器，形成有多个芯片支撑部分，并设置在印刷电路板的下方; 热连接层，其具有分别结合到散热器和印刷电路板的下金属层的下表面和上表面; 以及多个发光二极管芯片，其各自与芯片支撑部分中的一个接触并接合，并且每个芯片支撑部分电连接到上部电路层。 还公开了制造发光二极管模块的方法。