公开(公告)号：US20130214409A1

公开(公告)日：2013-08-22

申请号：US13845542

申请日：2013-03-18

Applicant: STATS CHIPPAC, LTD.

Inventor： Reza A. Pagaila ,  Rajendra D. Pendse ,  Jun Mo Koo

IPC: H01L23/28

CPC classification number: H01L23/28 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/18 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155

Abstract: A semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer includes a plurality of contact pads electrically continuous with the trace lines. A semiconductor die has a plurality of contact pads and bumps formed over the contact pads. A plurality of conductive pillars can be formed over the contact pads of the semiconductor die. The bumps are formed over the conductive pillars. The semiconductor die is mounted to the conductive layer with the bumps directly bonded to an end portion of the trace lines to provide a fine pitch interconnect. An encapsulant is deposited over the semiconductor die and conductive layer. The conductive layer contains wettable material to reduce die shifting during encapsulation. The carrier is removed. An interconnect structure is formed over the encapsulant and semiconductor die. An insulating layer can be formed over the conductive layer.

Abstract translation: 半导体管芯具有包括形成在载体上的多条迹线的导电层。 导电层包括与迹线相连接的多个接触垫。 半导体管芯具有形成在接触焊盘上的多个接触焊盘和凸块。 可以在半导体管芯的接触焊盘上形成多个导电柱。 凸块形成在导电柱上。 将半导体管芯安装到导电层上，凸块直接接合到迹线的端部，以提供细间距互连。 密封剂沉积在半导体管芯和导电层上。 导电层包含可湿性材料，以减少封装期间的模具移动。 载体被移除。 在密封剂和半导体管芯上形成互连结构。 可以在导电层上形成绝缘层。

公开(公告)号：US20130214398A1

公开(公告)日：2013-08-22

申请号：US13846014

申请日：2013-03-18

Applicant: STATS CHIPPAC, LTD.

Inventor： Reza A. Pagaila ,  Dioscoro A. Merilo

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/561 ,  H01L23/495 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die.

Abstract translation: 半导体器件具有带有第一和第二相对表面的基底基板。 在基底基板的第一表面上形成第一耐蚀刻导电层。 第二耐蚀刻导电层形成在基底衬底的第二表面上。 第一半导体管芯具有形成在第一管芯的有效表面上的接触焊盘上的凸起。 第一管芯安装在第一导电层的第一表面上。 密封剂沉积在第一管芯和基底衬底上。 去除基底衬底的一部分以在第一和第二导电层的相对部分之间形成电隔离的底部引线。 第二半导体管芯安装在密封剂上方，第一导电层的第二表面位于基底引线之间。 基部引线的高度大于第二管芯的厚度。

公开(公告)号：US20130207247A1

公开(公告)日：2013-08-15

申请号：US13845329

申请日：2013-03-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Rui Huang ,  Yaojian Lin

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.

Abstract translation: 通过在衬底上形成互连结构来制造半导体器件。 将半导体管芯安装到互连结构。 半导体管芯与互连结构电连接。 在互连结构上形成接地焊盘。 在半导体管芯和互连结构上形成密封剂。 在形成密封剂之前，可以在半导体管芯上方形成屏蔽笼。 在形成互连结构之后，在密封剂之上形成屏蔽层，以便相对于器件间干扰来隔离半导体管芯。 屏蔽层符合密封剂的几何形状并且电连接到接地垫。 屏蔽层可以通过导电柱电连接到地面。 在互连结构上形成背面互连结构，与半导体管芯相对。

公开(公告)号：US20130175696A1

公开(公告)日：2013-07-11

申请号：US13782618

申请日：2013-03-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。

公开(公告)号：US20130140719A1

公开(公告)日：2013-06-06

申请号：US13728012

申请日：2012-12-27

Applicant: Stats ChipPac, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu ,  Wei Meng ,  Chee Siang Ong

IPC: H01L23/29

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Abstract translation: 半导体器件具有沉积在半导体管芯上的半导体管芯和密封剂。 在管芯和密封剂上形成第一绝缘层。 第一绝缘层通过多个停留周期固化，以增强与管芯和密封剂的粘合性。 在第一绝缘层上方形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 第二绝缘层通过多个停留循环固化，以增强对第一绝缘层和第一导电层的粘合性。 在第二绝缘层和第一导电层上形成第二导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 第一，第二和第三绝缘层具有不同的CTE。 第二绝缘层或第三绝缘层固化至致密状态以阻止水分。

公开(公告)号：US20130105989A1

公开(公告)日：2013-05-02

申请号：US13715424

申请日：2012-12-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Seng Guan Chow ,  Seung Uk Yoon

IPC: H01L23/538

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24101 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/27002 ,  H01L2224/29 ,  H01L2224/2902 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/186 ,  H05K3/007 ,  H05K2201/10674 ,  H01L2224/81 ,  H01L2924/01014 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Abstract translation: 半导体器件具有安装在载体上的第一半导体管芯。 插入器框架在插入器框架中具有开口，并且在内插器框架上形成多个导电柱。 插入器安装在载体上，并且第一管芯与设置在管芯周围的导电柱相连。 可以在插入器框架中形成空腔以容纳第一模具的一部分。 密封剂通过载体和第一模具上的插入器框架中的开口沉积。 或者，密封剂沉积在载体上并且第一模头和插入器框架被压靠在密封剂上。 过多的密封剂通过插入器框架中的开口离开。 载体被移除。 在密封剂和第一模具上形成互连结构。 第二半导体管芯可以安装在第一管芯上方或内插架框架上。

公开(公告)号：US20130093068A1

公开(公告)日：2013-04-18

申请号：US13706818

申请日：2012-12-06

Applicant: Stats ChipPAC, Ltd.

Inventor： Reza A. Pagaila

IPC: H01L23/552 ,  H01L23/34 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/34 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device is made by mounting an insulating layer over a temporary substrate. A via is formed through the insulating layer. The via is filled with conductive material. A semiconductor die has a stress sensitive region. A dam is formed around the stress sensitive region. The semiconductor die is mounted to the conductive via. The dam creates a gap adjacent to the stress sensitive region. An encapsulant is deposited over the semiconductor die. The dam blocks the encapsulant from entering the gap. The temporary substrate is removed. A first interconnect structure is formed over the semiconductor die. The gap isolates the stress sensitive region from the first interconnect structure. A shielding layer or heat sink can be formed over the semiconductor die. A second interconnect structure can be formed over the semiconductor die opposite the first interconnect structure.

Abstract translation: 半导体器件通过将绝缘层安装在临时衬底上而制成。 通过绝缘层形成通孔。 通孔填充有导电材料。 半导体管芯具有应力敏感区域。 在压力敏感区域周围形成一个坝。 半导体管芯安装在导电通孔上。 大坝在应力敏感区域附近产生间隙。 密封剂沉积在半导体管芯上。 大坝堵塞密封剂进入间隙。 移除临时衬底。 第一互连结构形成在半导体管芯上。 间隙将应力敏感区域与第一互连结构隔离。 可以在半导体管芯上形成屏蔽层或散热器。 可以在与第一互连结构相对的半导体管芯上形成第二互连结构。

公开(公告)号：US20130075903A1

公开(公告)日：2013-03-28

申请号：US13684055

申请日：2012-11-21

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Seng Guan Chow ,  Seung Uk Yoon

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/82 ,  H01L2224/81

Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. Wettable contact pads can be formed over the carrier. A second semiconductor die is mounted over the first semiconductor die. The second die is laterally offset with respect to the first die. An electrical interconnect is formed between an overlapping portion of the first die and second die. A plurality of first conductive pillars is disposed over the first die. A plurality of second conductive pillars is disposed over the second die. An encapsulant is deposited over the first and second die and first and second conductive pillars. A first interconnect structure is formed over the encapsulant, first conductive pillars, and second die. The carrier is removed. A second interconnect structure is formed over the encapsulant, second conductive pillars, and first die. A third conductive pillar is formed between the first and second build-up interconnect structures.

Abstract translation: 半导体器件具有安装在载体上的第一半导体管芯。 可以在载体上形成可润湿的接触垫。 第二半导体管芯安装在第一半导体管芯上。 第二模具相对于第一模具横向偏移。 在第一管芯和第二管芯的重叠部分之间形成电互连。 多个第一导电柱设置在第一管芯上方。 多个第二导电柱设置在第二管芯上。 密封剂沉积在第一和第二管芯以及第一和第二导电柱上。 在密封剂，第一导电柱和第二模上形成第一互连结构。 载体被移除。 在密封剂，第二导电柱和第一模上形成第二互连结构。 在第一和第二堆积互连结构之间形成第三导电柱。

公开(公告)号：US20130026628A1

公开(公告)日：2013-01-31

申请号：US13645397

申请日：2012-10-04

Applicant: STATS CHIPPAC, LTD.

Inventor： Rajendra D. Pendse

IPC: H01L21/60 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/8121 ,  H01L2224/81211 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip chip interconnect of a die on a substrate is made by mating the interconnect bump onto a narrow interconnect pad on a lead or trace, rather than onto a capture pad. The width of the narrow interconnect pad is less than a base diameter of bumps on the die to be attached. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having narrow interconnect pads on electrically conductive traces in a die attach surface, in which the bumps are mated onto the narrow pads on the traces.

Abstract translation: 通过将互连凸块配合到引线或迹线上的窄互连焊盘而不是捕获板上，来制造衬底上的管芯的倒装芯片互连。 窄互连焊盘的宽度小于要连接的裸片上的凸块的基底直径。 此外，倒装芯片封装包括具有附着到有源表面中的互连焊盘的焊料凸块的芯片，以及在芯片附着表面中的导电迹线上具有窄互连焊盘的衬底，其中凸块配合到 痕迹

公开(公告)号：US20130015555A1

公开(公告)日：2013-01-17

申请号：US13622280

申请日：2012-09-18

Applicant: STATS chipPAC, lTD.

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang

IPC: H01L29/02

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is removed over the first contact pad, but not from the second contact pad. A conductive layer is formed over the first contact pad. The conductive layer is coiled on the surface of the substrate to produce inductive properties. The formation of the conductive layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the protective layer. The protective layer is removed from the second contact pad after forming the conductive layer over the first contact pad. An external connection is formed on the second contact pad.

Abstract translation: 半导体器件具有在其表面上形成有电感器的基板。 第一和第二接触垫形成在基板上。 在衬底和第一和第二接触焊盘之上形成钝化层。 在钝化层上形成保护层。 保护层在第一接触垫上移除，但不从第二接触垫移除。 导电层形成在第一接触焊盘上。 导电层被卷绕在基板的表面上以产生电感性质。 导电层的形成涉及使用湿蚀刻剂。 第二接触垫被保护层从湿蚀刻剂保护。 在第一接触垫上形成导电层之后，从第二接触焊盘去除保护层。 在第二接触垫上形成外部连接。