公开(公告)号：US06884655B2

公开(公告)日：2005-04-26

申请号：US10709912

申请日：2004-06-04

Applicant: Takahiro Iljima ,  Akio Rokugawa ,  Noriyoshi Shimizu

Inventor： Takahiro Iljima ,  Akio Rokugawa ,  Noriyoshi Shimizu

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/12 ,  H01L23/498 ,  H01L23/64 ,  H05K1/16 ,  H01L21/44 ,  H01L21/50

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/642 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0209 ,  H05K2201/09763 ,  H05K2203/135 ,  Y10S428/901

Abstract: A wiring layer for serving as a first electrode layer of a capacitor portion patterned in a predetermined shape on an insulative base member is formed. A resin layer for serving as a dielectric layer of the capacitor portion is formed on a surface of the wiring layer using an electrophoretic process. Another wiring layer for serving as a second electrode layer of the capacitor portion patterned in a predetermined shape by patterning on the insulative base member inclusive of the resin layer is formed.

Abstract translation: 形成用作在绝缘基底构件上以预定形状图案化的电容器部分的第一电极层的布线层。 使用电泳工艺在布线层的表面上形成用作电容器部分的介电层的树脂层。 形成另一布线层，用于通过在包括树脂层的绝缘基底上进行图案化而以预定形状图案化的电容器部分的第二电极层。

公开(公告)号：US20050063135A1

公开(公告)日：2005-03-24

申请号：US10664638

申请日：2003-09-18

Applicant: William Borland ,  Xin Fang

Inventor： William Borland ,  Xin Fang

IPC: H01G4/01 ,  H01G4/255 ,  H05K1/09 ,  H05K1/16 ,  H05K3/22 ,  H05K3/42 ,  H05K3/46 ,  H01G4/005

CPC classification number: H01G4/01 ,  H01G4/255 ,  H05K1/092 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2203/107 ,  H05K2203/171 ,  H05K2203/175

Abstract: In a printed wiring board, capacitors have electrode layers that may be selectively trimmed to obtain high tolerances. The electrode layers can be formed from a plurality of elongated electrode portions, each of which can be selectively trimmed. The electrode layers can also be formed from interdigitated elongated electrode portions.

公开(公告)号：US20050057867A1

公开(公告)日：2005-03-17

申请号：US10958442

申请日：2004-10-05

Applicant: Edwin Harris ,  Tushar Vyas ,  Timothy Pachla ,  James Colby

Inventor： Edwin Harris ,  Tushar Vyas ,  Timothy Pachla ,  James Colby

IPC: H02H9/04 ,  H05K1/00 ,  H05K1/02 ,  H05K1/16 ,  H02H9/00

CPC classification number: H01C7/12 ,  H01G2/14 ,  H02H9/044 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/0738 ,  H05K2201/09763

Abstract: A voltage variable material (“VVM”) including an insulative binder that is formulated to intrinsically adhere to conductive and non-conductive surfaces is provided. The binder and thus the VVM is self-curable and applicable in a spreadable form that dries before use. The binder eliminates the need to place the VVM in a separate device or to provide separate printed circuit board pads on which to electrically connect the VVM. The binder and thus the VVM can be directly applied to many different types of substrates, such as a rigid FR-4 laminate, a polyimide, a polymer or a multilayer PCB via a process such as screen or stencil printing. In one embodiment, the VVM includes two types of conductive particles, one with a core and one without a core. The VVM can also have core-shell type semiconductive particles.

Abstract translation: 提供了包括被配制为固有地粘附到导电和非导电表面的绝缘粘合剂的电压可变材料（“VVM”）。 粘合剂和因此VVM是自固化型和适用在使用前，其干燥可涂抹的形式。 粘合剂消除了将VVM放置在单独的装置中的需要，或者提供用于电连接VVM的单独的印刷电路板焊盘。 粘合剂和因此的VVM可以通过诸如筛网或模版印刷的工艺直接应用于许多不同类型的基材，例如刚性FR-4层压板，聚酰亚胺，聚合物或多层PCB。 在一个实施例中，VVM包括两种类型的导电颗粒，其中一个芯和一个没有芯。 VVM还可以具有核 - 壳型半导体颗粒。

公开(公告)号：US20050012217A1

公开(公告)日：2005-01-20

申请号：US10497536

申请日：2003-12-10

Applicant: Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

Inventor： Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

IPC: H01L23/498 ,  H05K1/03 ,  H05K1/16 ,  H05K3/00 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/0366 ,  H05K1/162 ,  H05K3/0041 ,  H05K3/0044 ,  H05K3/388 ,  H05K3/4061 ,  H05K3/4069 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/09763 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/1338 ,  H05K2203/1581 ,  Y10T29/43 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

Abstract translation: 在层叠在所述芯板的一个表面上的芯板，布线层和电绝缘层的多层布线基板中，所述芯板的XY方向的热膨胀系数在2〜20ppm的范围内 所述芯板的核心部件是选自硅，陶瓷，玻璃，玻璃 - 环氧复合材料和金属的核心部件，所述芯板设置有多个在正面和背面之间导电的通孔 通过导电材料，并且在所述芯板的一个表面上设置电容器，其中所述电容器包括在所述通孔中作为导电材料的上电极和设置成经由电介质层面对所述上电极的下电极 。

公开(公告)号：US06803324B2

公开(公告)日：2004-10-12

申请号：US10240330

申请日：2003-03-06

Applicant: Tsuyoshi Ogawa ,  Yuji Nishitani ,  Akihiko Okubora

Inventor： Tsuyoshi Ogawa ,  Yuji Nishitani ,  Akihiko Okubora

IPC: H01L21469

CPC classification number: H05K3/4682 ,  H01L21/4846 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1531 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K1/0237 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/095 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/183 ,  H05K3/0052 ,  H05K3/20 ,  H05K3/205 ,  H05K3/4605 ,  H05K3/4614 ,  H05K3/4644 ,  H05K3/467 ,  H05K3/4688 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/016 ,  H05K2203/061 ,  H05K2203/1189 ,  H01L2924/00

Abstract: A wiring circuit block is produced by forming a release layer on one of planarized principal surfaces of a mother substrate, forming an insulating layer on the release layer, patterning the insulating layer and forming a wiring layer on the patterned insulating layer, and separating the insulating layer and wiring layer from the release layer on the mother substrate. The circuit block has components, and deposited on the wiring layer, and is mounted on a base circuit board to provide a wiring device. Also, semiconductor chips are mounted on the circuit block, and the circuit block is mounted on a base circuit board to provide a semiconductor device.

Abstract translation: 通过在母基板的平坦化主面之一上形成剥离层，在剥离层上形成绝缘层，对绝缘层进行图案化，在图案化绝缘层上形成布线层，分离绝缘层而制造布线电路块 层和布线层从母基板上的释放层。 电路块具有部件并且沉积在布线层上，并且安装在基板电路板上以提供布线装置。 此外，半导体芯片安装在电路块上，并且电路块安装在基极电路板上以提供半导体器件。

公开(公告)号：US20040144476A1

公开(公告)日：2004-07-29

申请号：US10753535

申请日：2004-01-09

Inventor： Junzo Fukuta ,  Satoru Adachi

IPC: C03B029/00

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/167 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4688 ,  H05K2201/09763 ,  H05K2203/061 ,  H05K2203/171 ,  Y10T29/49112 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49162 ,  Y10T29/49163 ,  H01L2924/00

Abstract: After a resistor and/or a capacitor are simultaneously fired on a fired ceramic core substrate to be fired, the fired resistor and/or the fired capacitor is trimmed so that the resistance and the capacitance are adjusted. Thereafter, an after-lamination green sheet is laminated onto the ceramic core substrate and the produced after-lamination substrate is fired at a temperature which is lower than the sintering temperature of the resistor and the dielectric. Thus, the sintered resistor and dielectric can be prevented from being softened and melted when the after-lamination substrate is fired. Moreover, the resistance and the capacitance accurately adjusted by trimming before the after-lamination substrate is fired are not changed by the firing.

Abstract translation: 在烧结的烧结陶瓷芯基板上同时点燃电阻器和/或电容器之后，对烧结的电阻器和/或烧结电容器进行微调，以便调节电阻和电容。 然后，在陶瓷芯基板上层压分层后的生片，在低于电阻体和电介质的烧结温度的温度下烧制所制造的叠层后基板。 因此，烧结的电阻体和电介质可以防止在后层压衬底被烧制时软化和熔化。 此外，烧结之前通过在叠层后基板被修整而精确调节的电阻和电容不会因烧制而改变。

公开(公告)号：US06731495B2

公开(公告)日：2004-05-04

申请号：US10285748

申请日：2002-11-01

Applicant: Prabhat Kumar ,  Henning Uhlenhut

Inventor： Prabhat Kumar ,  Henning Uhlenhut

IPC: H01G420

CPC classification number: H01G9/15 ,  H01G4/10 ,  H01G11/48 ,  H05K1/162 ,  H05K2201/0179 ,  H05K2201/0329 ,  H05K2201/09763 ,  Y02E60/13

Abstract: The invention relates to a thin film capacitor containing (a) a substrate, (b) a first polymeric film containing an electrically conductive polymer located on the substrate, (c) a pentoxide layer selected from the group consisting of tantalum pentoxide, or niobium pentoxide, and mixtures thereof, (d) a second polymeric film containing an electrically conductive polymer located on the pentoxide layer.

Abstract translation: 本发明涉及一种薄膜电容器，其包含（a）基底，（b）含有位于基底上的导电聚合物的第一聚合物膜，（c）选自五氧化二钽或五氧化二铌的五氧化物层 ，及其混合物，（d）含有位于五氧化物层上的导电聚合物的第二聚合物膜。

公开(公告)号：US06631551B1

公开(公告)日：2003-10-14

申请号：US09105611

申请日：1998-06-26

Applicant: Philip Harbaugh Bowles ,  Washington Morris Mobley ,  Richard Dixon Parker ,  Marion Edmond Ellis

Inventor： Philip Harbaugh Bowles ,  Washington Morris Mobley ,  Richard Dixon Parker ,  Marion Edmond Ellis

IPC: H01C1706

CPC classification number: H05K1/162 ,  H01C7/003 ,  H01C7/005 ,  H01C17/065 ,  H01G4/33 ,  H05K1/092 ,  H05K1/095 ,  H05K1/167 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/0338 ,  Y10T29/49099 ,  Y10T29/49155 ,  Y10T29/49158

Abstract: A process for forming stable integrated resistors (14) and capacitors (28) on organic substrates (12). The resistors (14) and capacitors (28) are capable of a wide range of resistance and capacitance values, yet can be processed in a manner that does not detrimentally effect the organic substrate (12) or entail complicated processing. The method generally entails the use of thick-film materials usually of the types used to form resistors and capacitors on ceramic substrates. The thick-film materials are applied to an electrically-conductive foil (20) and then heated to bond the thick-film material to the foil (20) and form a solid resistive or capacitive mass (16/30). The foil (20) is then laminated to an organic substrate (12), such that the resistive/capacitive mass (16/30) is attached to and preferably embedded in the organic substrate (12). Finally, the foil (20) is etched to form at least one of two terminals that contact the resistive/capacitive mass (16/30) and thereby complete the passive electrical component (14/28). Resistors (14) can also be formed of polymer thick-film (PTF) inks, in which case the PTF ink is cured on the foil (20) for an extended period at a temperature sufficient to completely cure the ink prior to laminating the foil (20) to the organic substrate (12).

公开(公告)号：US20030112110A1

公开(公告)日：2003-06-19

申请号：US10246151

申请日：2002-09-17

Inventor： Mark Pavier

IPC: H01F027/02

CPC classification number: H05K1/165 ,  H01F17/0006 ,  H01F17/043 ,  H01L23/645 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H05K3/429 ,  H05K2201/086 ,  H05K2201/09763 ,  H05K2203/0545

Abstract: An embedded inductor which includes a spiral conductive inductor embedded in a magnetically permeable body composed of particles of pre-sintered magnetically permeable (e.g. ferromagnetic) material and an epoxy binder.

Abstract translation: 一种嵌入式电感器，其包括嵌入由预烧结的导磁（例如铁磁）材料和环氧树脂粘合剂的颗粒组成的导磁体中的螺旋导电电感器。

公开(公告)号：US20030097750A1

公开(公告)日：2003-05-29

申请号：US10078448

申请日：2002-02-21

Applicant: Hitachi, Ltd.

Inventor： Hiroshi Okabe ,  Hirozi Yamada ,  Eriko Takeda ,  Kazunori Yamamoto ,  Hiroyuki Kuriya ,  Masanori Yamaguchi ,  Kazuhisa Otsuka ,  Yoshitaka Hirata ,  Yasushi Shimada

IPC: H05K003/20

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/162 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0338 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a manufacturing method of an electronic circuit device including a multi-layer circuit board incorporated with a thin film capacitor small in size and of high performance capable of attaining higher capacitance value with a thin dielectric film of high dielectric constant and with favorable film quality. A first electrode layer and a thin film dielectric layer are laminated continuously in this order in one identical to laminate each of the layers on a leveled substrate in one identical chamber and then the first electrode layer is fabricated a conductor pattern.

Abstract translation: 本发明提供一种电子电路器件的制造方法，该电子电路器件包括多层电路板，该多层电路板结合有小型和高性能的薄膜电容器，能够用高介电常数的薄电介质膜获得较高的电容值 电影质量。 将第一电极层和薄膜电介质层依次层叠在一个相同的层中，在一个相同的室中的层叠基板上层叠，然后将第一电极层制成导体图案。