公开(公告)号：US07277005B2

公开(公告)日：2007-10-02

申请号：US11022074

申请日：2004-12-22

Applicant: Myung Sam Kang ,  Chang Sup Ryu ,  Jong Kuk Hong

Inventor： Myung Sam Kang ,  Chang Sup Ryu ,  Jong Kuk Hong

IPC: H01C1/012

CPC classification number: H01C7/003 ,  H01C17/065 ,  H01C17/0652 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/167 ,  H05K3/0047 ,  H05K3/005 ,  H05K3/4069 ,  H05K3/42 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09645 ,  H05K2203/1476

Abstract: Disclosed is a PCB including an embedded resistor and a method of fabricating the same. The PCB includes a plurality of circuit layers in which circuit patterns are formed. A plurality of insulating layers is each interposed between the circuit layers. The embedded resistor is made of a resistive material and received in a receiving hole formed in the plurality of circuit layers and the plurality of insulating layers such that walls defining the receiving hole extends from one of the circuit layers to another circuit layer. The receiving hole has a closed section, and a conductive material is plated on the opposite walls of the walls defining the receiving hole.

Abstract translation: 公开了一种包括嵌入式电阻器的PCB及其制造方法。 PCB包括形成电路图案的多个电路层。 在电路层之间分别插入多个绝缘层。 嵌入式电阻器由电阻材料制成并且被容纳在形成在多个电路层和多个绝缘层中的接收孔中，使得限定接收孔的壁从电路层之一延伸到另一个电路层。 接收孔具有闭合部分，并且导电材料被电镀在限定接收孔的壁的相对壁上。

公开(公告)号：US20070132536A1

公开(公告)日：2007-06-14

申请号：US11637664

申请日：2006-12-13

Applicant: Doo-Hwan Lee ,  Byoung-Youl Min ,  Myung-Sam Kang ,  Moon-Il Kim ,  Hyung-Tae Kim

Inventor： Doo-Hwan Lee ,  Byoung-Youl Min ,  Myung-Sam Kang ,  Moon-Il Kim ,  Hyung-Tae Kim

IPC: H01F5/00

CPC classification number: H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/056 ,  H05K3/4608 ,  H05K2201/10515 ,  Y10T29/4913 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A printed circuit board having embedded electronic components and a manufacturing method thereof are disclosed. With the printed circuit board having embedded electronic components, including a core sheet, a first electronic component mounted on one side of the core sheet, a second electronic component mounted on the other side of the core sheet and overlapping the first electronic component, a first insulation layer stacked on one side of the core sheet and covering the first electronic component, a second insulation layer stacked on the other side of the core sheet and covering the second electronic component, and a circuit pattern formed on the surface of the first insulation layer or the second insulation layer, the density of the printed circuit board having embedded components is improved, as a plurality of electronic components are embedded simultaneously, and when a thin CCL substrate or a metal substrate is used as the core, a metal substrate in particular, the heat-releasing property and mechanical strength are improved, including increased bending strength in a thermal-stress environment, as electronic components are mounted on both sides of the core sheet.

Abstract translation: 公开了一种具有嵌入式电子部件的印刷电路板及其制造方法。 利用具有嵌入式电子部件的印刷电路板，包括芯片，安装在芯片的一侧的第一电子部件，安装在芯片的另一侧并与第一电子部件重叠的第二电子部件，第一电子部件 绝缘层，其堆叠在所述芯片的一侧并覆盖所述第一电子部件;堆叠在所述芯片的另一侧并覆盖所述第二电子部件的第二绝缘层，以及形成在所述第一绝缘层的表面上的电路图案 或第二绝缘层，随着多个电子部件被同时嵌入，具有嵌入部件的印刷电路板的密度得到改善，并且当使用薄CCL基板或金属基板作为芯时，特别是金属基板 ，提高了散热性能和机械强度，包括在热应力环境中增加弯曲强度 因为电子部件安装在芯片的两侧。

公开(公告)号：US20070065986A1

公开(公告)日：2007-03-22

申请号：US11524402

申请日：2006-09-21

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC: H01L21/00

CPC classification number: H05K3/4652 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/183 ,  H05K3/205 ,  H05K3/4697 ,  H05K2201/09536 ,  H05K2203/0574 ,  H05K2203/063 ,  H05K2203/308 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015

Abstract: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit pattern on one side of a seed layer by use of a first dry film; (b) laminating a second dry film on the first dry film, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer. The method in accordance with the present invention can mount a plurality of integrated circuits by reducing the thickness of a substrate on a package on package.

Abstract translation: 公开了一种用于制造具有空腔的衬底的方法。 该方法包括：（a）通过使用第一干膜在种子层的一侧上形成第一电路图案; （b）在第一干膜上层压第二干膜，第二干膜的厚度对应于待形成的空腔的深度; （c）在要形成空腔的区域外的区域上层叠电介质层，所述电介质层的厚度对应于待形成的空腔的深度; （d）在种子层上层叠具有第二电路图案的铜箔层叠主板; 和（e）通过在去除种子层之后剥离第一干膜和第二干膜来形成空腔。 根据本发明的方法可以通过减小封装上的封装上的衬底的厚度来安装多个集成电路。

公开(公告)号：US20060017435A1

公开(公告)日：2006-01-26

申请号：US10975736

申请日：2004-10-28

Applicant: Myung-Sam Kang ,  Chang-Sup Ryu ,  Won-Cheol Bae ,  Sang-Duck Kim ,  Doo-Hwan Lee

Inventor： Myung-Sam Kang ,  Chang-Sup Ryu ,  Won-Cheol Bae ,  Sang-Duck Kim ,  Doo-Hwan Lee

IPC: G01R33/02

CPC classification number: G01R33/04 ,  H05K1/165 ,  H05K3/4641 ,  H05K3/4652 ,  H05K2201/086 ,  H05K2201/10151

Abstract: A Printed Circuit Board (PCB) having a weak magnetic field sensor of the present invention includes a base plate on which a first excitation circuit and a first detection circuit are formed on each of the sides thereof, soft magnetic core bodies laminated on the top and bottom of the base plate, respectively, and formed of a plurality of soft magnetic cores, and outer layers that are laminated on the soft magnetic core bodies, respectively, and on which a second excitation circuit and a second detection circuit connected to the first excitation circuit and the first detection circuit through via holes are formed so as to surround the soft magnetic cores, respectively. The present invention is characterized in that the soft magnetic cores, the excitation circuit and the detection circuit formed on one side of the base plate are perpendicular to the soft magnetic cores, the excitation circuit and the detection circuit formed on the other side of the base plate.

Abstract translation: 本发明的具有弱磁场传感器的印刷电路板（PCB）包括：基板，其基板在其基板上形成有第一激励电路和第一检测电路，软磁芯体层叠在顶板上， 底板分别由多个软磁芯和层叠在软磁体上的外层构成，第二激励电路和第二检测电路分别连接到第一激励 电路和通过通孔的第一检测电路分别形成为围绕软磁芯。 本发明的特征在于，形成在基板的一侧上的软磁芯，激励电路和检测电路垂直于软磁芯，激励电路和检测电路形成在基座的另一侧 盘子。

公开(公告)号：US20060001422A1

公开(公告)日：2006-01-05

申请号：US10965613

申请日：2004-10-14

Applicant: Myung-Sam kang ,  Chang-Sup Ryu ,  Won-Cheol Bae ,  Jae-Kul Lee ,  Doo-Hwan Lee

Inventor： Myung-Sam kang ,  Chang-Sup Ryu ,  Won-Cheol Bae ,  Jae-Kul Lee ,  Doo-Hwan Lee

IPC: G01R33/00

CPC classification number: G01R33/04 ,  H05K1/165 ,  H05K3/4641 ,  H05K3/4652 ,  H05K2201/086 ,  H05K2201/10151

Abstract: Disclosed is a printed circuit board with a weak magnetic field sensor according to the present invention, which includes a substrate having first excitation circuits and first detection circuits formed on both sides thereof. First laminates are layered on both sides of the substrate, and have soft magnetic cores with a predetermined shape formed thereon. Second laminates are layered on the first laminates, and have second excitation circuits and second detection circuits, connected through via holes to the first excitation circuits and first detection circuits, respectively, so that the first and second excitation circuits and first and second detection circuits are wound around the soft magnetic cores, formed thereon. The soft magnetic cores each include a magnetic core and non-magnetic metal layers formed on both sides of the magnetic core.

Abstract translation: 公开了根据本发明的具有弱磁场传感器的印刷电路板，其包括具有形成在其两侧上的第一激励电路和第一检测电路的基板。 第一层压体层叠在基板的两侧，并且具有形成在其上的预定形状的软磁芯。 第二层叠体层叠在第一层叠体上，并具有分别通过通孔与第一激励电路和第一检测电路连接的第二激励电路和第二检测电路，使得第一和第二激励电路以及第一和第二检测电路 缠绕在其上形成的软磁芯上。 软磁芯各自包括形成在磁芯两侧的磁芯和非磁性金属层。

公开(公告)号：US20050172480A1

公开(公告)日：2005-08-11

申请号：US11061611

申请日：2005-02-22

Applicant: Won-youl Choi ,  Keon-yang Park ,  Byeong-cheon Koh ,  Myung-sam Kang ,  Kyung-won Na ,  Sang-on Choi

Inventor： Won-youl Choi ,  Keon-yang Park ,  Byeong-cheon Koh ,  Myung-sam Kang ,  Kyung-won Na ,  Sang-on Choi

IPC: G01R33/02 ,  G01R33/04 ,  G01R33/05 ,  H01L43/00 ,  H01L21/00 ,  B32B31/26 ,  G01R31/00 ,  H01F7/06

CPC classification number: G01R33/05 ,  G01R15/185 ,  G01R33/04 ,  Y10T29/49073 ,  Y10T29/49075

Abstract: A fluxgate sensor integrated in a printed circuit board. The fluxgate sensor has soft magnetic cores having a lower core and an upper core mounted on the lower core, for forming a closed magnetic path on a printed circuit board, an excitation coil formed as a metal film, alternately winding the upper and the lower soft magnetic cores substantially in a number ‘8’ pattern, and a pick-up coil formed as a metal film, having a structure of winding the upper and the lower soft magnetic cores substantially in a solenoid pattern, the pick-up coil being placed on the same plane as an external contour of the excitation coil.

Abstract translation: 集成在印刷电路板中的磁通门传感器。 磁通门传感器具有软磁芯，其具有安装在下芯上的下芯和上芯，用于在印刷电路板上形成闭合磁路，形成为金属膜的励磁线圈，交替地卷绕上软和下软 基本上为“8”图案的磁芯和形成为金属膜的拾取线圈，其具有将上下软磁芯卷绕成螺线管图案的结构，拾取线圈被放置在 与激励线圈的外部轮廓相同的平面。

公开(公告)号：US08633392B2

公开(公告)日：2014-01-21

申请号：US13354438

申请日：2012-01-20

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/02

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.

Abstract translation: 一种电路板，包括：具有沟槽的绝缘体; 形成为埋入沟槽的一部分的第一电路图案; 以及形成在其中形成有沟槽的绝缘体的表面上的第二电路图案。

公开(公告)号：US08546943B2

公开(公告)日：2013-10-01

申请号：US12923037

申请日：2010-08-30

Applicant: Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

Inventor： Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

IPC: H01L23/13 ,  H01L23/498

CPC classification number: H01L21/76885 ,  H01L21/02112 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Provided is a ball grid array substrate, a semiconductor chip package, and a method of manufacturing the same. The ball grid array substrate includes an insulating layer having a first surface providing a mounting region for a semiconductor chip, a second surface opposing the first surface, and an opening connecting the second surface with the mounting region of the semiconductor chip, and a circuit pattern buried in the second surface. Since the ball grid array substrate is manufactured by a method of stacking two insulating layers, existing devices can be used, and the ball grid array substrate can be manufactured as an ultra thin plate. In addition, since the circuit pattern is buried in the insulating layer, a high-density circuit pattern can be formed.

Abstract translation: 提供了一种球栅阵列基板，半导体芯片封装及其制造方法。 球栅阵列基板包括绝缘层，其具有提供半导体芯片的安装区域的第一表面，与第一表面相对的第二表面和连接第二表面与半导体芯片的安装区域的开口，以及电路图案 埋在第二面。 由于球栅阵列基板通过堆叠两个绝缘层的方法制造，因此可以使用现有的装置，并且可以将球栅阵列基板制造为超薄板。 此外，由于电路图案被埋在绝缘层中，因此可以形成高密度电路图案。

公开(公告)号：US08464423B2

公开(公告)日：2013-06-18

申请号：US13373387

申请日：2011-11-14

Applicant: Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

Inventor： Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

IPC: H01R9/00 ,  H01R43/16 ,  H01R43/00 ,  H05K3/00 ,  H05K3/02 ,  H05K3/10

CPC classification number: H05K1/111 ,  H05K1/09 ,  H05K1/115 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0323 ,  H05K2203/0376 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: A method of manufacturing a printed circuit board having a metal bump, including: forming a recess for creation of the metal bump on a first carrier, forming a first barrier layer on the first carrier, and forming an upper circuit layer on the first barrier layer, the upper circuit layer including a metal bump charged in the recess and a circuit pattern; forming a second barrier layer on a second carrier, and forming a lower circuit layer on the second barrier layer; preparing an insulating layer, and transferring the upper and lower circuit layers to the insulating layer; removing the first and second carriers; and removing the first and second barrier layers.

Abstract translation: 一种制造具有金属凸块的印刷电路板的方法，包括：在第一载体上形成用于形成金属凸块的凹部，在第一载体上形成第一阻挡层，并在第一阻挡层上形成上电路层 所述上电路层包括充电在所述凹部中的金属凸块和电路图案; 在第二载体上形成第二阻挡层，并在第二阻挡层上形成下电路层; 制备绝缘层，并将上下电路层转移到绝缘层; 移除第一和第二载体; 以及去除所述第一和第二阻挡层。

公开(公告)号：US08415200B2

公开(公告)日：2013-04-09

申请号：US13007444

申请日：2011-01-14

Applicant: Mi Sun Hwang ,  Keung Jin Sohn ,  Eung Suek Lee ,  Myung Sam Kang

Inventor： Mi Sun Hwang ,  Keung Jin Sohn ,  Eung Suek Lee ,  Myung Sam Kang

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H05K3/06 ,  H05K3/4038 ,  H05K3/4647 ,  H05K2203/0384 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed herein is a method for manufacturing a semiconductor package which uses a base member 120 in which a first metal layer 113, a barrier layer 115, and a second metal layer 117 are stacked on both surface thereof in sequence based on an adhesive member 111 to simultaneously manufacture two printed circuit boards through a single sheet process, thereby making it possible to improve manufacturing efficiency; electrically connects a semiconductor chip 300 to a printed circuit board through a solder bump 250, thereby making it possible to implement a high-density package substrate; and forms a metal post 140 instead of a through hole to required in an interlayer circuit connection, thereby making it possible to reduce costs required in the processing/plating of the through hole.

Abstract translation: 本发明公开了一种半导体封装件的制造方法，该半导体封装件使用基片120，其中第一金属层113，阻挡层115和第二金属层117依次以两个表面层叠在第一金属层113，阻挡层115和第二金属层117上， 同时通过单片工艺制造两个印刷电路板，从而可以提高制造效率; 通过焊料凸块250将半导体芯片300电连接到印刷电路板，从而可以实现高密度封装基板; 并且形成金属柱140而不是层间电路连接所需的通孔，从而可以降低通孔的加工/电镀所需的成本。