公开(公告)号：US20020070423A1

公开(公告)日：2002-06-13

申请号：US09998924

申请日：2001-11-29

Applicant: KYOCERA CORPORATION

Inventor： Junya Takafuji

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/16 ,  H05K1/162 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/467 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09763 ,  H01L2924/00

Abstract: An object of the invention is to provide a thin-film electronic component and a motherboard in which coupling strength of an external terminal to a supporting substrate is improved. The thin-film electronic component comprising: a supporting substrate; a lower electrode formed on part of the supporting substrate; an insulation layer formed on the lower electrode; an upper electrode formed on the insulation layer; a connection electrode which is formed on part of the supporting substrate located on a bottom surface of a through hole formed on the insulation layer, and is electrically connected to the lower electrode; and an external terminal disposed on the connection electrode within the through hole.

Abstract translation: 本发明的目的是提供一种薄膜电子部件和母板，其中外部端子与支撑基板的耦合强度得到改善。 所述薄膜电子部件包括：支撑基板; 形成在所述支撑基板的一部分上的下电极; 形成在下电极上的绝缘层; 形成在绝缘层上的上电极; 连接电极，其形成在位于形成在所述绝缘层上的通孔的底面上的所述支撑基板的一部分上，并且电连接到所述下电极; 以及设置在通孔内的连接电极上的外部端子。

公开(公告)号：US6005197A

公开(公告)日：1999-12-21

申请号：US918216

申请日：1997-08-25

Applicant: Ratnaji Roa Kola ,  Louis Thomas Manzione ,  Roderick Kent Watts

Inventor： Ratnaji Roa Kola ,  Louis Thomas Manzione ,  Roderick Kent Watts

IPC: B32B9/00 ,  H01L23/12 ,  H05K1/16 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2203/0315 ,  H05K3/429 ,  Y10T29/435 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The specification describes of multilevel printed circuit boards and a process for their manufacture in which capacitors and other passive components are buried between levels of the multilevel board. The capacitor in the multilevel structure is designed so that access is conveniently provided to connect from the parallel plate electrodes of the interlevel capacitor to the board surface or to another board level using plated through hole interconnects.

Abstract translation: 本说明书描述了多层印刷电路板及其制造方法，其中电容器和其它无源部件被埋在多层板的层级之间。 多层结构中的电容器被设计成使得通过电镀通孔互连方便地提供接入以从层间电容器的平行板电极到板表面或另一个板级连接。

公开(公告)号：US5874770A

公开(公告)日：1999-02-23

申请号：US731172

申请日：1996-10-10

Applicant: Richard Joseph Saia ,  Kevin Matthew Durocher ,  Herbert Stanley Cole

Inventor： Richard Joseph Saia ,  Kevin Matthew Durocher ,  Herbert Stanley Cole

IPC: H05K3/46 ,  H01L21/48 ,  H01L21/822 ,  H01L21/98 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L27/04 ,  H05K1/16 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H01L23/053 ,  H01L23/02 ,  H01L23/48

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/18 ,  H01L24/82 ,  H01L25/16 ,  H01L25/50 ,  H05K1/162 ,  H05K1/167 ,  H01L2224/18 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315 ,  H05K2203/0361 ,  H05K3/388 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4644 ,  Y10T29/49165

Abstract: A method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide. If the resistor and metallization layers are applied over both surfaces of the dielectric film, passive components can be fabricated on both surfaces of the dielectric film. The dielectric film can have vias therein with the resistor and metallization layers extending through the vias. A circuit chip can be attached and coupled to the passive components by metallization patterned through vias in an additional dielectric layer.

Abstract translation: 制造柔性互连膜的方法包括在电介质膜的一个或两个表面上施加电阻层; 在所述电阻层上施加金属化层，所述电阻层包括促进所述电介质膜和所述金属化层的粘附的材料; 在所述金属化层上施加电容器电介质层; 以及在电容器电介质层上施加电容器电极层。 将电容器电极层图案化以形成第一电容器电极; 对电容器电介质层进行图案化; 图案化金属化层以形成电阻器; 并且金属化层和电阻层被图案化以形成电感器和第二电容器电极。 在一个实施例中，电介质膜包括聚酰亚胺，电阻层包括氮化钽，电容器介电层包括无定形氢化碳或氧化钽。 如果将电阻和金属化层施加在电介质膜的两个表面上，则可以在电介质膜的两个表面上制造无源元件。 电介质膜可以具有通孔，其中电阻器和金属化层延伸穿过通孔。 电路芯片可以通过在附加电介质层中通过通孔图案化的金属化而附接并耦合到无源部件。

公开(公告)号：US5814366A

公开(公告)日：1998-09-29

申请号：US682410

申请日：1996-07-17

Applicant: Junzo Fukuta ,  Koji Shibata ,  Nozomi Tanifuji ,  Masaya Hashimoto ,  Yoshiaki Yamade ,  Hidenori Kataura

Inventor： Junzo Fukuta ,  Koji Shibata ,  Nozomi Tanifuji ,  Masaya Hashimoto ,  Yoshiaki Yamade ,  Hidenori Kataura

IPC: B32B18/00 ,  C04B35/645 ,  C04B41/90 ,  H01G4/12 ,  H01L21/48 ,  H01L23/538 ,  H01L23/64 ,  H05K1/03 ,  H05K1/16 ,  H05K3/46 ,  B05D5/12

CPC classification number: H05K1/162 ,  B32B18/00 ,  B32B37/26 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/5383 ,  H01L23/642 ,  B32B2309/02 ,  B32B2309/12 ,  B32B2315/02 ,  B32B9/04 ,  C04B2235/768 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/346 ,  C04B2237/562 ,  C04B2237/66 ,  C04B2237/68 ,  C04B35/645 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/167 ,  H05K2201/0187 ,  H05K2201/09763 ,  H05K3/4611 ,  H05K3/4629

Abstract: In a method of manufacturing a multilayered ceramic substrate, a capacitor layer is formed on a green sheet of a low temperature co-firable ceramic by means of printing. The green sheet with the capacitor layer and a plurality of other green sheets are laminated together into a substrate laminate. Two release green sheets of alumina system each unsintered below 1,000.degree. C. are further laminated to the top and the bottom of the substrate laminate respectively. The obtained laminate is fired at a temperature ranging between 800.degree. and 1,000.degree. C. under pressure ranging between 2 and 20 kgf/cm.sup.2. The release green sheets adherent to the side surfaces of the substrate are removed after the firing. Subsequently, a wiring pattern is printed on the substrate, which is then fired at a temperature ranging between 800.degree. and 1,000.degree. C.

Abstract translation: 在制造多层陶瓷基板的方法中，通过印刷在低温可共熔陶瓷的生片上形成电容器层。 将具有电容器层和多个其它生片的生片层叠在一起形成基板层叠体。 将两个未烧结在1000℃以下的氧化铝体系的两片释放生片进一步层压到基底层压板的顶部和底部。 将得到的层压体在800〜1000℃的温度范围内，在2〜20kgf / cm 2的压力范围内烧成。 在烧制之后，去除附着于基板侧表面的剥离生片。 接着，在基板上印刷布线图案，然后在800〜1000℃的温度下烧成。

公开(公告)号：US5796572A

公开(公告)日：1998-08-18

申请号：US616723

申请日：1996-03-15

Applicant: Wakahiro Kawai

Inventor： Wakahiro Kawai

IPC: H01G4/08 ,  H01G4/33 ,  H01L27/01 ,  H05K1/14 ,  H05K1/16 ,  H05K3/10 ,  H05K3/24 ,  H05K3/38 ,  H01G4/10 ,  H01G4/06

CPC classification number: H01G4/08 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09763 ,  H05K3/102 ,  H05K3/245 ,  H05K3/38 ,  H05K3/383 ,  Y10T29/43 ,  Y10T29/435

Abstract: A high-capacitance thin film capacitc is compact and has a low profile. A dielectric layer 3 is formed between opposed electrodes 1 and 2. Between the electrodes and the dielectric layer are two layers of conductive particles, 4 and 5.

Abstract translation: 高电容薄膜电容紧凑，外形小巧。 介电层3形成在相对的电极1和2之间。电极和电介质层之间是两层导电颗粒4和5。

公开(公告)号：US5726482A

公开(公告)日：1998-03-10

申请号：US319906

申请日：1994-10-07

Applicant: Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  Robert Osann, Jr.

Inventor： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  Paul Y. F. Wu ,  Robert Osann, Jr.

IPC: G01R1/04 ,  G01R1/06 ,  G01R31/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H01L29/00

CPC classification number: G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  H05K7/1092 ,  G01R1/06 ,  G01R31/2863 ,  H01L2924/0002 ,  H01R23/70 ,  H01R31/06 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

Abstract: A device-under-test card includes a matrix of fuses and/or antifuses formed as part of a multi-layered structure. The matrix of fuses and/or antifuses can be electrically programmed to connect any one of first electrical contacts to any one of second electrical contacts and so allows the device-under-test card to act as a junction between burn-in board traces couplable to signal drivers and/or receivers and burn-in board traces couplable to terminals of a device-under-test. The device-under-test card also includes a discrete resistor or alternatively a resistor ladder that permits a terminal of a device-under-test to be coupled to a power or ground terminal or to any combination of resistances including a short, in addition or as an alternative to any one of various signal drivers and/or receivers.

Abstract translation: 被测器件包括形成为多层结构的一部分的保险丝和/或反熔断矩阵。 保险丝和/或反熔丝的矩阵可以被电编程以将第一电触点中的任何一个连接到第二电触点中的任一个，并且因此允许测试下的卡作为可连接到 信号驱动器和/或接收器以及可以连接到被测器件端子的老化板迹线。 测试卡以下的设备还包括分立电阻器或可选的电阻梯，其允许被测器件的端子耦合到电源或接地端子或电阻的任何组合，包括短路，或另外 作为各种信号驱动器和/或接收器中的任何一个的替代。

公开(公告)号：US5573808A

公开(公告)日：1996-11-12

申请号：US589234

申请日：1996-01-22

Applicant: Werner Gruenwald ,  Walter Roethlingshoefer ,  Ulrich Goebel ,  Ralf Haug ,  Manfred Moser ,  Annette Seibold

Inventor： Werner Gruenwald ,  Walter Roethlingshoefer ,  Ulrich Goebel ,  Ralf Haug ,  Manfred Moser ,  Annette Seibold

IPC: H01G4/30 ,  H01L21/48 ,  H01L23/538 ,  H05K1/09 ,  H05K1/16 ,  H05K3/20 ,  H05K3/46 ,  B05D5/12 ,  B41M3/12

CPC classification number: H05K1/162 ,  H01G4/30 ,  H01L21/4857 ,  H01L23/5383 ,  H01L2924/0002 ,  H05K1/092 ,  H05K2201/09236 ,  H05K2201/09763 ,  H05K3/207 ,  H05K3/4611 ,  H05K3/4629 ,  Y10T29/435

Abstract: In a method for producing a multilayer circuit, it is possible to produce capacitor structures including electrodes and a dielectric arranged in between. By pressing the capacitor structures into a ceramic layer, it is possible to produce a high-quality capacitor inside the multilayer circuit.

Abstract translation: 在制造多层电路的方法中，可以制造包括电极和布置在其间的电介质的电容器结构。 通过将电容器结构压入陶瓷层，可以在多层电路内产生高质量的电容器。

公开(公告)号：US5572409A

公开(公告)日：1996-11-05

申请号：US319860

申请日：1994-10-07

Applicant: Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang

Inventor： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang

IPC: G01R1/04 ,  G01R1/06 ,  G01R31/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H05K7/06 ,  H01R9/09

CPC classification number: G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  H05K7/1092 ,  G01R1/06 ,  G01R31/2863 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01R23/70 ,  H01R31/06 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable socket adapter in one embodiment. The socket adapter can be used for interconnecting an electronic component having terminals in a first configuration to electrical contacts in printed circuit board.

Abstract translation: 在一个实施例中，公开了两种类型的可编程元件，熔丝和反熔丝，用于形成电可编程插座适配器。 插座适配器可用于将具有第一配置的端子的电子部件与印刷电路板中的电触点相互连接。

公开(公告)号：US4302737A

公开(公告)日：1981-11-24

申请号：US105946

申请日：1979-12-20

Applicant: Helmold Kausche ,  Heinz Hebbeker

Inventor： Helmold Kausche ,  Heinz Hebbeker

IPC: H01C17/24 ,  H01C13/02 ,  H01C17/242 ,  H01G4/255 ,  H01L27/01 ,  H03H1/02 ,  H03H7/06 ,  H05K1/00 ,  H05K1/16 ,  H05K3/02 ,  H03H3/00 ,  H03H7/01

CPC classification number: H05K1/162 ,  H01C13/02 ,  H01C17/242 ,  H01L27/01 ,  H05K1/0393 ,  H05K1/167 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H05K2203/171 ,  H05K3/027 ,  Y10T29/49082 ,  Y10T29/49099

Abstract: An RC network is disclosed in which two electrically conducting regions and a dielectric lying between these regions form a capacitor. At least one of the electrically conducting regions consists of resistance material and is designed in the shape of a meandering path. This network can be balanced while still guaranteeing a uniform region distribution of the resistance and the capacitance, by means of a laser beam. Upon a carrier of heat-resistant material, a resistance layer, a dielectric of glow discharge polymer, and an opposite electrode capable of regeneration, are applied. The dielectric completely covers the resistance layer with the exception of contact pads.

Abstract translation: 公开了一种RC网络，其中两个导电区域和位于这些区域之间的电介质形成电容器。 至少一个导电区域由电阻材料构成，并且被设计成曲折路径的形状。 该网络可以平衡，同时通过激光束保证电阻和电容的均匀区域分布。 在耐热材料的载体上施加电阻层，辉光放电聚合物的电介质和能够再生的相对电极。 电介质完全覆盖电阻层，接触垫除外。

公开(公告)号：US3996502A

公开(公告)日：1976-12-07

申请号：US582955

申请日：1975-06-02

Applicant: William R. Bratschun

Inventor： William R. Bratschun

IPC: H01G4/06 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K3/28 ,  H05K3/46 ,  H01G4/12

CPC classification number: H05K1/162 ,  H01G4/06 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/09763 ,  H05K3/28 ,  H05K3/4667

Abstract: An alumina substrate thick film circuit includes capacitors sealed with two intermediate layers of non-conductive material and two layers of sealing glass. The temperature coefficient of expansion of the sealing glass is less than that of the substrate. The temperature coefficient of expansion of the intermediate layer material is intermediate those of the substrate and the sealing glass, or equal to that of the sealing glass.

Abstract translation: 氧化铝基板厚膜电路包括用两层中间层非导电材料和两层密封玻璃密封的电容器。 密封玻璃的温度膨胀系数小于基板的温度系数。 中间层材料的温度系数与基板和密封玻璃的温度系数相当，或等于密封玻璃的温度系数。