公开(公告)号：US20140126169A1

公开(公告)日：2014-05-08

申请号：US14062264

申请日：2013-10-24

Applicant: NITTO DENKO CORPORATION

Inventor： Terukazu IHARA ,  Jun ISHII ,  Naohiro TERADA

IPC: H05K7/02 ,  H05K3/10

CPC classification number: H05K3/10 ,  G11B5/486 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0265 ,  H05K1/056 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/4685 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2203/0323 ,  Y10T29/49155

Abstract: A plurality of suspension boards and an inspection substrate are integrally supported by a support frame. In each suspension board, a line is formed on a conductive first support substrate via a first insulating layer. The first support substrate and the line are electrically connected by a first via in the first insulating layer. In the inspection substrate, a conductor layer is formed on a conductive second support substrate with a second insulating layer sandwiched therebetween. The second support substrate and the conductor layer are electrically connected by a second via in the second insulating layer. The first via and the second via have the same configuration.

Abstract translation: 多个悬挂板和检查基板由支撑框架一体地支撑。 在每个悬挂板中，经由第一绝缘层在导电的第一支撑基板上形成线。 第一支撑基板和线通过第一绝缘层中的第一通孔电连接。 在检查基板中，导电层形成在导电性的第二支撑基板上，其间夹着第二绝缘层。 第二支撑基板和导体层通过第二绝缘层中的第二通孔电连接。 第一通孔和第二通孔具有相同的配置。

公开(公告)号：US20140026412A1

公开(公告)日：2014-01-30

申请号：US13948642

申请日：2013-07-23

Applicant: IBIDEN Co., Ltd.

Inventor： Naoto ISHIDA

IPC: H05K3/40 ,  H05K3/10

CPC classification number: H05K3/4038 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/10 ,  H05K3/4602 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for manufacturing a printed wiring board includes forming on a support sheet an intermediate body including a first insulation layer, a second insulation layer and a first conductive layer interposed between the first insulation layer and the second insulation layer, and separating the support sheet from the intermediate body including the insulation layer, the first conductive layer and the second insulation layer such that the intermediate body is detached from the support sheet.

Abstract translation: 一种制造印刷电路板的方法，包括在支撑片上形成中间体，该中间体包括第一绝缘层，第二绝缘层和介于第一绝缘层和第二绝缘层之间的第一导电层，并将支撑片从 所述中间体包括所述绝缘层，所述第一导电层和所述第二绝缘层，使得所述中间体与所述支撑片分离。

公开(公告)号：US08622751B2

公开(公告)日：2014-01-07

申请号：US13392933

申请日：2010-08-17

Applicant: Juergen Lappoehn

Inventor： Juergen Lappoehn

IPC: H01R12/00

CPC classification number: H01R12/727 ,  H01R13/658 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/308 ,  H05K3/3426 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10189

Abstract: The invention relates to a multi-pole plug connector (90) for contacting a multi-layer circuit board (51), comprising a plurality of contact elements (50a, 50b-50′a, 50′b), as well as to a multi-layer circuit board for assembly with a multi-pole plug connector (90), comprising blind boreholes (60a, 60b-60′a, 60′b) for contacting terminal pins (53a, 53b-53′a, 53′b) of the contact elements (50a, 50b-50′a, 50′b) of the multi-pole plug connector (90). The invention further relates to a combination of a multi-pole plug connector (90) for contacting with a multi-layer circuit board (51) and to a multilayer circuit board for assembly with the multi-pole plug connector (90). The plug connector (90) according to the invention is characterized by terminal pins (53a, 53b-53′a, 53′b) that have different lengths for contacting the terminal pins (53a, 53b-53′a, 53′b) with conductors (52a, 52b; 72a, 72b-72′a, 72′b) of the multi-layer circuit board (51) provided in different conductor levels (71-71′). The multi-layer circuit board (51) according to the invention is characterized by blind boreholes (60a, 60b-60′a, 60′b) that terminate in different conductor levels (71-71′) of the multilayer circuit board (51) for deliberately contacting the terminal pins (53a, 53b-53′a, 53′b) with conductors (52a, 52b; 72a, 72b-72′a, 72′b) of the multilayer circuit board (51) provided in different conductor levels (71-71′).

Abstract translation: 本发明涉及一种用于接触包括多个接触元件（50a，50b-50'a，50'b）的多层电路板（51）的多极插头连接器（90），以及一个 用于与多极插头连接器（90）组装的多层电路板，包括用于接触端子销（53a，53b-53'a，53'b）的盲孔（60a，60b-60'a，60'b） ）多极插头连接器（90）的接触元件（50a，50b-50'a，50'b）。 本发明还涉及用于与多层电路板（51）接触的多极插头连接器（90）和用于与多极插头连接器（90）组装的多层电路板的组合。 根据本发明的插头连接器（90）的特征在于具有用于接触端子销（53a，53b-53'a，53'b）的不同长度的端子销（53a，53b-53'a，53'b） 其中多层电路板（51）的导体（52a，52b; 72a，72b-72'a，72'b）设置在不同的导体电平（71-71'）中。 根据本发明的多层电路板（51）的特征在于终止于多层电路板（51）的不同导体水平（71-71'）的盲孔（60a，60b-60'a，60'b） ）用于将端子销（53a，53b-53'a，53'b）与设置在不同的多层电路板（51）的导体（52a，52b; 72a，72b-72'a，72'b）故意接触 导体水平（71-71'）。

公开(公告)号：US20130341073A1

公开(公告)日：2013-12-26

申请号：US13864278

申请日：2013-04-17

Applicant: ZHEN DING TECHNOLOGY CO., LTD.

Inventor： CHE-WEI HSU ,  SHIH-PING HSU

IPC: H05K3/40 ,  H05K3/00 ,  H05K1/11

CPC classification number: H05K3/4038 ,  H01L21/486 ,  H01L23/5387 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/118 ,  H05K3/0094 ,  H05K3/243 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0989 ,  H05K2201/099 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A packaging substrate includes an insulating layer, a wiring layer and a solder mask. The insulating layer and the solder mask being arranged on two opposite sides of the wiring layer. The insulating layer defines a via hole. The wiring layer covers the via hole. The wiring layer includes a pad area. Two sides of the pad area are respectively exposed outside from the solder mask and in the via hole.

Abstract translation: 封装衬底包括绝缘层，布线层和焊接掩模。 绝缘层和焊料掩模布置在布线层的两个相对侧上。 绝缘层限定通孔。 布线层覆盖通孔。 布线层包括焊盘区域。 焊盘区域的两侧分别从焊接面罩和通孔露出。

公开(公告)号：US08613136B2

公开(公告)日：2013-12-24

申请号：US12614576

申请日：2009-11-09

Applicant: Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

Inventor： Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

IPC: H01K3/10

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/188 ,  H05K3/382 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract translation: 通过提供具有第一绝缘层和导电膜的层叠体的方法制造印刷线路板。 通过去除导电膜的至少一部分，在层压体中形成对准标记。 将电子部件放置在基于对准标记确定的位置上设置在第一绝缘层上的粘合剂层上。 在将电子部件封装在第二绝缘层的开口内之后，在基于用于确定电子部件的位置的对准标记确定的位置处形成暴露电子部件的端子的通孔。 通孔导体形成在通孔中，导电层形成在导电膜上并被图案化以形成连接到通孔导体的导电电路。

公开(公告)号：US08563420B2

公开(公告)日：2013-10-22

申请号：US13561247

申请日：2012-07-30

Applicant: Takashi Kariya ,  Akira Mochida

Inventor： Takashi Kariya ,  Akira Mochida

IPC: H01L21/4763

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body.

Abstract translation: 一种制造印刷电路板的方法包括在第一金属层上形成含有原料陶瓷材料的未煅烧层，焙烧形成在第一金属层上的未煅烧层，使得具有以片状形式煅烧的陶瓷体的高介电常数层 形成在第一金属层上，相对于第一金属层在高介电常数层的相对侧的高介电常数层上形成第二金属层，使得具有高介电常数层的层状电容器和第一金属层 形成夹着高介电常数层的第二层电极，并将层叠电容器配置在主体中。

公开(公告)号：US08551812B2

公开(公告)日：2013-10-08

申请号：US13352647

申请日：2012-01-18

Applicant: Ming Yi Yeh ,  Jia Lin Liu ,  Chung Shih Wu

Inventor： Ming Yi Yeh ,  Jia Lin Liu ,  Chung Shih Wu

IPC: H01L21/00

CPC classification number: H05K3/4691 ,  H05K3/4652 ,  H05K2201/09509 ,  Y10T156/1056

Abstract: In a manufacturing method of a printed circuit board, a rigid substrate having a rigid-board metal layer is provided, an open slot is formed on the rigid substrate, and a flexible substrate is installed in the open slot, and the flexible substrate and the rigid substrate are securely bonded, and an increased-layer circuit layer is formed after electric circuits are manufactured on the rigid-board and flexible-board metal layers, and stacked on the rigid substrate and on an adjacent block where the flexible substrate is coupled to the rigid substrate, and an electric circuit is manufactured, and the increased-layer circuit layer is provided for electrically connecting and conducting the rigid and flexible substrates to overcome the issue of alignment errors.

Abstract translation: 在印刷电路板的制造方法中，设置具有刚性基板金属层的刚性基板，在刚性基板上形成开放槽，将柔性基板安装在开放槽内，柔性基板和 刚性基板牢固地结合，并且在刚性板和柔性板金属层上制造电路之后形成增加层的电路层，并堆叠在刚性基板上以及在柔性基板耦合到的相邻块上 制造刚性基板和电路，并且提供增加层电路层用于电连接和导电刚性和柔性基板以克服对准误差的问题。

公开(公告)号：US08536696B2

公开(公告)日：2013-09-17

申请号：US12546950

申请日：2009-08-25

Applicant: Naohiro Hirose ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

Inventor： Naohiro Hirose ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

IPC: H01L23/12 ,  H01L21/00 ,  H05K7/00

CPC classification number: H01L23/49811 ,  H01L2224/05001 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/15312 ,  H05K1/111 ,  H05K1/112 ,  H05K3/28 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/09381 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/10318 ,  Y10T428/239

Abstract: A package substrate including an outermost interlayer resin insulating layer, a pad structure formed on the outermost interlayer resin insulating layer, a conductive connecting pin for establishing an electrical connection with another substrate, the conductive connecting pin being secured to the pad structure via a solder, and via holes formed through the outermost interlayer resin insulating layer and for electrically connecting the pad structure to one or more conductive circuits formed below the outermost interlayer resin insulating layer, the via holes being positioned directly below the pad structure.

Abstract translation: 包括最外层间树脂绝缘层，形成在最外层间树脂绝缘层上的焊盘结构的封装基板，用于与另一基板建立电连接的导电连接引脚，所述导电连接引脚通过焊料固定在焊盘结构上， 以及通过最外层间树脂绝缘层形成的通孔，并且将焊盘结构电连接到在最外层间树脂绝缘层下形成的一个或多个导电电路，通孔位于焊盘结构的正下方。

公开(公告)号：US08536463B2

公开(公告)日：2013-09-17

申请号：US12923997

申请日：2010-10-20

Applicant: Mitsuharu Shoji ,  Kiwamu Adachi

Inventor： Mitsuharu Shoji ,  Kiwamu Adachi

IPC: H05K3/02 ,  H05K3/10 ,  H05K1/16

CPC classification number: H05K1/162 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/125

Abstract: A method for manufacturing a printed-circuit board including: a capacitive element forming step of embedding a capacitive element in a substrate resin layer inside a substrate that includes a plurality of wiring layers laminated with the substrate resin layer interposed in between, the capacitive element forming step including forming a lower electrode using a conductive layer on one of the plurality of wiring layers, or using one of the plurality of wiring layers; forming a crystalline metal oxide-containing capacitor dielectric film at a temperature at or below a heat-resistant temperature of the substrate resin layer, and at or above room temperature; and forming an upper electrode on an upper surface of the capacitor dielectric film on the side opposite to the lower electrode.

Abstract translation: 一种印刷电路板的制造方法，其特征在于，包括：电容元件形成步骤，将电容元件嵌入到基板内部的基板树脂层内，所述基板包括与介于其间的基板树脂层层叠的多个布线层，所述电容元件形成 包括在所述多个布线层之一上使用导电层形成下电极，或者使用所述多个布线层中的一个布线层; 在等于或低于衬底树脂层的耐热温度或低于室温的温度下形成含结晶金属氧化物的电容器电介质膜; 以及在所述电容器电介质膜的与所述下电极相反的一侧的上表面上形成上电极。

公开(公告)号：US08492659B2

公开(公告)日：2013-07-23

申请号：US12379295

申请日：2009-02-18

Applicant: Kenji Nagase ,  Hiroyuki Uematsu ,  Kenichi Kawabata

Inventor： Kenji Nagase ,  Hiroyuki Uematsu ,  Kenichi Kawabata

IPC: H05K1/11

CPC classification number: H05K3/0035 ,  H05K1/115 ,  H05K3/0055 ,  H05K3/381 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/0557 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The present invention provides a printed wiring board which can prevent a plating failure in a connection hole such as a via to be formed in the printed wiring board, thereby can enhance the connection reliability and a manufacturing method therefor. The printed wiring board 100 includes a thermosetting resin sheet 16 (insulation layer) having a via hole 20 (through hole) constituted by inner wall parts having different taper angles from each other, a copper foil 17 (conductor layer) provided on the thermosetting resin sheet 16, and a wiring pattern 13 (wiring layer) which is provided so as to be exposed from the via hole 20 and is electrically connected with the copper foil 17 through the via hole 20.