公开(公告)号：US08279616B2

公开(公告)日：2012-10-02

申请号：US13064541

申请日：2011-03-30

Applicant: Han Kim ,  Je-Gwang Yoo ,  Mi-Ja Han ,  Dae-Hyun Park

Inventor： Han Kim ,  Je-Gwang Yoo ,  Mi-Ja Han ,  Dae-Hyun Park

IPC: H05K1/18

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/0236 ,  H05K1/165 ,  H05K1/185 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09663 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: A printed circuit board having an embedded chip capacitor includes a first conductive layer; a second conductive layer, placed away from the first conductive layer; a chip capacitor, having a first electrode connected to the first conductive layer through being seated in a cavity formed between the first conductive layer and the second conductive layer; a filled material, filled in a space excluding a space occupied by the chip capacitor in the cavity; and a via, penetrating the filled material and connecting the second conductive layer to the second electrode of the chip capacitor.

Abstract translation: 具有嵌入式芯片电容器的印刷电路板包括：第一导电层; 远离所述第一导电层放置的第二导电层; 芯片电容器，其具有通过位于形成在第一导电层和第二导电层之间的空腔中而连接到第一导电层的第一电极; 填充材料，填充在空腔内不包括由片状电容器占据的空间的空间中; 以及通孔，穿透填充材料并将第二导电层连接到片式电容器的第二电极。

公开(公告)号：US20120217647A9

公开(公告)日：2012-08-30

申请号：US13207633

申请日：2011-08-11

Applicant: Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/18 ,  H01L24/19 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract translation: 半导体器件具有形成在半导体晶片的有源表面上的保护层。 具有预先施加的保护层的半导体管芯从半导体晶片移动并安装在载体上。 载体上的半导体管芯和接触焊盘被封装。 载体被移除。 在预先施加的保护层和接触垫上形成第一绝缘层。 在第一绝缘层和预先施加的保护层中形成通孔以暴露半导体管芯上的互连部位。 在第一绝缘层上形成互连结构，与半导体管芯和接触焊盘上的互连部位电接触。 互连结构具有形成在第一绝缘层上的再分布层，形成在再分配层上的第二绝缘层和形成在与再分布层电接触的第二电介质上的凸块下金属化层。

公开(公告)号：US08247289B2

公开(公告)日：2012-08-21

申请号：US11508141

申请日：2006-08-23

Applicant: Yoshiki Yamanishi ,  Muneo Harada ,  Takahiro Kitano ,  Tatsuzo Kawaguchi ,  Yoshihiro Hirota ,  Kinji Yamada ,  Tomotaka Shinoda ,  Katsuya Okumura ,  Shuichi Kawano

Inventor： Yoshiki Yamanishi ,  Muneo Harada ,  Takahiro Kitano ,  Tatsuzo Kawaguchi ,  Yoshihiro Hirota ,  Kinji Yamada ,  Tomotaka Shinoda ,  Katsuya Okumura ,  Shuichi Kawano

IPC: H01L21/8242 ,  H01L21/20 ,  H01L21/00

CPC classification number: H01L23/50 ,  H01G4/228 ,  H01G4/33 ,  H01L23/481 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/162 ,  H05K3/002 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/10378

Abstract: A capacitor having a high quality and a manufacturing method of the same are provided.A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.

Abstract translation: 提供了具有高质量的电容器及其制造方法。 电容器具有形成在氧化膜上的下电极，形成在下电极上的电介质层，形成为与电极之间介电层相对的下电极的上电极和形成为覆盖上电极的上电极 ，上电极的开口部分和电介质层的开口部分。 通过在电介质层上形成上电极，可以通过使用上电极作为掩模对电介质层进行图案化，并且通过防止杂质扩散到电介质层中来提供具有高质量电介质层的电容器。 通过在电介质层上形成上部电极，可以防止电介质层暴露于蚀刻液体，液体显影剂等

公开(公告)号：US20120184115A1

公开(公告)日：2012-07-19

申请号：US13392933

申请日：2010-08-17

Applicant: Juergen Lappoehn

Inventor： Juergen Lappoehn

IPC: H01R12/71 ,  H05K1/11

CPC classification number: H01R12/727 ,  H01R13/658 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/308 ,  H05K3/3426 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10189

Abstract: The invention relates to a multi-pole plug connector (90) for contacting a multi-layer circuit board (51), comprising a plurality of contact elements (50a, 50b-50′a, 50′b), as well as to a multi-layer circuit board for assembly with a multi-pole plug connector (90), comprising blind boreholes (60a, 60b-60′a, 60′b) for contacting terminal pins (53a, 53b-53′a, 53′b) of the contact elements (50a, 50b-50′a, 50′b) of the multi-pole plug connector (90). The invention further relates to a combination of a multi-pole plug connector (90) for contacting with a multi-layer circuit board (51) and to a multilayer circuit board for assembly with the multi-pole plug connector (90). The plug connector (90) according to the invention is characterized by terminal pins (53a, 53b-53′a, 53′b) that have different lengths for contacting the terminal pins (53a, 53b-53′a, 53′b) with conductors (52a, 52b; 72a, 72b-72′a, 72′b) of the multi-layer circuit board (51) provided in different conductor levels (71-71′). The multi-layer circuit board (51) according to the invention is characterized by blind boreholes (60a, 60b-60′a, 60′b) that terminate in different conductor levels (71-71′) of the multilayer circuit board (51) for deliberately contacting the terminal pins (53a, 53b-53′a, 53′b) with conductors (52a, 52b; 72a, 72b-72′a, 72′b) of the multilayer circuit board (51) provided in different conductor levels (71-71′).

Abstract translation: 本发明涉及一种用于接触包括多个接触元件（50a，50b-50'a，50'b）的多层电路板（51）的多极插头连接器（90），以及一个 用于与多极插头连接器（90）组装的多层电路板，包括用于接触端子销（53a，53b-53'a，53'b）的盲孔（60a，60b-60'a，60'b） ）多极插头连接器（90）的接触元件（50a，50b-50'a，50'b）。 本发明还涉及用于与多层电路板（51）接触的多极插头连接器（90）和用于与多极插头连接器（90）组装的多层电路板的组合。 根据本发明的插头连接器（90）的特征在于具有用于接触端子销（53a，53b-53'a，53'b）的不同长度的端子销（53a，53b-53'a，53'b） 其中多层电路板（51）的导体（52a，52b; 72a，72b-72'a，72'b）设置在不同的导体电平（71-71'）中。 根据本发明的多层电路板（51）的特征在于终止于多层电路板（51）的不同导体水平（71-71'）的盲孔（60a，60b-60'a，60'b） ）用于将端子销（53a，53b-53'a，53'b）与设置在不同的多层电路板（51）的导体（52a，52b; 72a，72b-72'a，72'b）故意接触 导体水平（71-71'）。

公开(公告)号：US08222534B2

公开(公告)日：2012-07-17

申请号：US12076118

申请日：2008-03-13

Applicant: Jun-Heyoung Park ,  Jee-Soo Mok ,  Ki-Hwan Kim ,  Sung-Yong Kim

Inventor： Jun-Heyoung Park ,  Jee-Soo Mok ,  Ki-Hwan Kim ,  Sung-Yong Kim

IPC: H05K1/11 ,  H05K3/02

CPC classification number: H05K3/4614 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4647 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/061 ,  Y10T29/49156

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The method of manufacturing a printed circuit board, by forming at least one bump for interlayer conduction on a surface of a board and stacking an insulation layer on the surface of the board, can include the operations of forming at least one dam on the surface of the board that surrounds a region corresponding to the bump, forming the bump by printing conductive paste onto the region corresponding to the bump, and stacking the insulation layer onto the surface of the board. This method can be utilized to improve productivity and resolve the problem of spreading.

Abstract translation: 公开了印刷电路板和印刷电路板的制造方法。 制造印刷电路板的方法通过在基板的表面上形成至少一个用于层间导电的凸块并在该表面上堆叠绝缘层的方法可以包括在表面上形成至少一个坝的操作 围绕与凸块相对应的区域的板，通过将导电膏印刷到对应于凸块的区域上形成凸块，并将绝缘层堆叠到板的表面上。 该方法可用于提高生产力并解决传播问题。

公开(公告)号：US20120106032A1

公开(公告)日：2012-05-03

申请号：US13345227

申请日：2012-01-06

Applicant: John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Anthony P. Chacko ,  Gregory J. Dunn

Inventor： John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Anthony P. Chacko ,  Gregory J. Dunn

IPC: H01G9/025 ,  H01G9/04 ,  H01G9/15 ,  H01G7/00

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G9/042 ,  H01G9/045 ,  H01G9/15 ,  H05K3/429 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09909 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/435

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract translation: 一种用于形成具有电容的叠层的方法和由此形成的层压体。 该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。 在电介质上形成导电层。 处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。 在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。

公开(公告)号：US20120104628A1

公开(公告)日：2012-05-03

申请号：US13347683

申请日：2012-01-10

Applicant: Chin Hock TOH ,  Yao Huang HUANG ,  Ravi Kanth KOLAN ,  Wei Liang YUAN ,  Susanto TANARY ,  Yi Sheng Anthony SUN

Inventor： Chin Hock TOH ,  Yao Huang HUANG ,  Ravi Kanth KOLAN ,  Wei Liang YUAN ,  Susanto TANARY ,  Yi Sheng Anthony SUN

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L21/563 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K3/3478 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/10378 ,  H05K2203/043 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.

Abstract translation: 介绍了插件。 插入器包括具有第一和第二表面的插入器基座。 再分配层设置在插入器基座的第一表面上。 插入器具有耦合到再分配层的至少一个插入器焊盘。 它还包括在第二表面上的至少一个中介层接触。 插入器触点通过再分配层电耦合到插入器衬垫。 插入器还包括通过插入器基座的至少一个插入器，用于将插入器触点耦合到再分配层。 插入器通孔包括内插器接触件的回流导电材料。

公开(公告)号：US08124880B2

公开(公告)日：2012-02-28

申请号：US11976207

申请日：2007-10-22

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/03

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

Abstract translation: 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

公开(公告)号：US08116066B2

公开(公告)日：2012-02-14

申请号：US12366140

申请日：2009-02-05

Applicant: Osamu Inoue

Inventor： Osamu Inoue

IPC: H01G4/06

CPC classification number: H01L23/5389 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/0035 ,  H05K3/06 ,  H05K3/061 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10636 ,  H05K2201/10643 ,  H05K2201/10674 ,  H05K2203/1152 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599

Abstract: In a method of manufacturing an electronic component built-in substrate of the present invention, a mounted body including a first insulating layer, a stopper metal layer formed under the first insulating layer of a portion corresponding to a component mounting region and a second insulating layer formed on a lower surface of the first insulating layer and covering the stopper metal layer is prepared, and a concave portion is obtained by penetration-processing a portion of the first insulating layer, which corresponds to the component mounting region to form an opening portion, while using the stopper metal layer as a stopper. Also, the stopper metal layer in the concave portion is removed, then an electronic component is mounted on the concave portion, and then a third insulating layer is formed on the electronic component.

Abstract translation: 在本发明的电子部件内置基板的制造方法中，具有第一绝缘层，形成在对应于部件安装区域的部分的第一绝缘层下方的止动金属层的安装体和第二绝缘层 形成在第一绝缘层的下表面上并覆盖止动金属层，并且通过对与元件安装区域相对应的第一绝缘层的一部分进行穿透处理而形成凹部以形成开口部， 同时使用塞子金属层作为塞子。 此外，去除凹部中的止动金属层，然后将电子部件安装在凹部上，然后在电子部件上形成第三绝缘层。

公开(公告)号：US20120028459A1

公开(公告)日：2012-02-02

申请号：US12873540

申请日：2010-09-01

Applicant: Yu-Yong Lee ,  Sung-Mo Kang ,  Soon-Heung Bae ,  Chang-Suk Han

Inventor： Yu-Yong Lee ,  Sung-Mo Kang ,  Soon-Heung Bae ,  Chang-Suk Han

IPC: H01L21/768

CPC classification number: H05K3/4652 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/429 ,  H05K2201/09509 ,  H01L2924/00

Abstract: A manufacturing process of a circuit substrate is provided. A conductive structure including a first patterned conductive layer, a first dielectric layer, a second dielectric layer, a first conductive layer, and a second conductive layer is provided. The first dielectric layer and the second dielectric layer are respectively disposed on two opposite surfaces of the first patterned conductive layer. The first conductive layer and the second conductive layer are respectively disposed on the first dielectric layer and the second dielectric layer. The first dielectric layer is between the first patterned conductive layer and the first conductive layer. The second dielectric layer is between the first patterned conductive layer and the second conductive layer. A conductive via is formed at the conductive structure. The first conductive layer and the second conductive layer are patterned to respectively form a second patterned conductive layer and a third patterned conductive layer.

Abstract translation: 提供电路基板的制造工艺。 提供包括第一图案化导电层，第一介电层，第二介电层，第一导电层和第二导电层的导电结构。 第一电介质层和第二电介质层分别设置在第一图案化导电层的两个相对的表面上。 第一导电层和第二导电层分别设置在第一介电层和第二介电层上。 第一介电层位于第一图案化导电层和第一导电层之间。 第二介电层位于第一图案化导电层和第二导电层之间。 在导电结构处形成导电通孔。 图案化第一导电层和第二导电层以分别形成第二图案化导电层和第三图案化导电层。