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31.
公开(公告)号:US20180094361A1
公开(公告)日:2018-04-05
申请号:US15724909
申请日:2017-10-04
Applicant: OSAKA UNIVERSITY , ITOCHU PLASTICS INC.
Inventor: Yusuke MORI , Masashi YOSHIMURA , Mamoru IMADE , Masayuki IMANISHI , Akira KITAMOTO , Masashi ISEMURA
CPC classification number: C30B29/403 , C30B25/165 , C30B25/18 , H01L21/02389 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/0262
Abstract: The present invention provides a method for producing a Group III nitride crystal that can produce a Group III nitride crystal of high quality with few defects such as crack, dislocation, and the like by vapor phase epitaxy. In order to achieve the above object, the method for producing a Group III nitride crystal of the present invention includes a step of: causing Group III element-containing gas 111a to react with nitrogen-containing gas 203a and 203b to generate a Group III nitride crystal 204, wherein in the Group III nitride crystal generation step, the reaction is performed in the presence of a carbon-containing substance.
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公开(公告)号:US09917422B2
公开(公告)日:2018-03-13
申请号:US14721729
申请日:2015-05-26
Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Inventor: Po Shan Hsu , Kathryn M. Kelchner , Robert M. Farrell , Daniel A. Haeger , Hiroaki Ohta , Anurag Tyagi , Shuji Nakamura , Steven P. DenBaars , James S. Speck
IPC: H01S5/00 , H01S5/343 , B82Y20/00 , H01L21/02 , H01S5/32 , H01L31/0304 , H01L31/036 , H01L31/0735 , H01L33/00 , H01L33/06 , H01L33/16 , H01L33/32 , H01S5/20 , H01S5/22 , H01S5/30 , H01S5/34
CPC classification number: H01S5/34333 , B82Y20/00 , H01L21/02389 , H01L21/02433 , H01L21/0254 , H01L21/02609 , H01L31/03044 , H01L31/036 , H01L31/0735 , H01L33/0025 , H01L33/0045 , H01L33/06 , H01L33/16 , H01L33/32 , H01S5/0014 , H01S5/2009 , H01S5/2031 , H01S5/22 , H01S5/3063 , H01S5/3202 , H01S5/3404 , H01S2304/04
Abstract: An optoelectronic device grown on a miscut of GaN, wherein the miscut comprises a semi-polar GaN crystal plane (of the GaN) miscut x degrees from an m-plane of the GaN and in a c-direction of the GaN, where −15
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公开(公告)号:US20180066378A1
公开(公告)日:2018-03-08
申请号:US15696269
申请日:2017-09-06
Applicant: TOYODA GOSEI CO., LTD.
Inventor: Miki MORIYAMA , Shiro YAMAZAKI , Yasuhide YAKUSHI
CPC classification number: C30B19/02 , C23C16/34 , C23C16/45525 , C23C16/56 , C30B19/12 , C30B29/406 , H01L21/02389 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02625 , H01L21/02628 , H01L21/02642 , H01L21/02647 , H01L21/7813
Abstract: To reduce ungrown region or abnormal grain growth region in growing a Group III nitride semiconductor through a flux method. A seed substrate has a structure in which a Group III nitride semiconductor layer is formed on a ground substrate as a base, and a mask is formed on the Group III nitride semiconductor layer. The mask has a plurality of dotted windows in an equilateral triangular lattice pattern. A Group III nitride semiconductor is grown through flux method on the seed substrate. Carbon is placed on a lid of a crucible holing the seed substrate and a molten mixture so that carbon is not contact with the molten mixture at the start of crystal growth. Thereby, carbon is gradually added to the molten mixture as time passes. Thus, ungrown region or abnormal grain growth region is reduced in the Group III nitride semiconductor crystal grown on the seed substrate.
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34.
公开(公告)号:US20180057960A1
公开(公告)日:2018-03-01
申请号:US15800128
申请日:2017-11-01
Applicant: Mitsubishi Chemical Corporation
Inventor: Yuuki ENATSU , Satoru NAGAO , Shuichi KUBO , Hirotaka IKEDA , Kenji FUJITO
CPC classification number: C30B29/406 , C30B25/02 , C30B25/14 , C30B25/20 , C30B29/403 , H01L21/02389 , H01L21/02433 , H01L21/0254 , H01L21/0262 , H01L21/02634 , H01L29/2003
Abstract: A periodic table Group 13 metal nitride crystals grown with a non-polar or semi-polar principal surface have numerous stacking faults. The purpose of the present invention is to provide a period table Group 13 metal nitride crystal wherein the occurrence of stacking faults of this kind are suppressed. The present invention achieves the foregoing by a periodic table Group 13 metal nitride crystal being characterized in that, in a Qx direction intensity profile that includes a maximum intensity and is derived from an isointensity contour plot obtained by x-ray reciprocal lattice mapping of (100) plane of the periodic table Group 13 metal nitride crystal, a Qx width at 1/300th of peak intensity is 6×10−4 rlu or less.
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公开(公告)号:US09896780B2
公开(公告)日:2018-02-20
申请号:US14905559
申请日:2014-07-25
Applicant: STANLEY ELECTRIC CO., LTD.
Inventor: Hiroshi Furuya , Toshiyuki Obata
CPC classification number: C30B25/186 , C30B25/20 , C30B29/403 , H01L21/02043 , H01L21/02389 , H01L21/0242 , H01L21/0243 , H01L21/0254 , H01L21/02598 , H01L21/0262 , H01L21/02658
Abstract: Provided is a method for pretreatment of a group III nitride single crystal substrate having a high Al composition ratio, for manufacturing a high-quality group III nitride thin film.The method includes heating the base substrate at a temperature range of 1000 to 1250° C. for no less than 5 minutes under a first mixed gas atmosphere before a layer of a second group III nitride single crystal is grown, wherein the first mixed gas includes hydrogen gas and nitrogen gas; the base substrate includes a layer of a first group III nitride single crystal at least on a surface of the base substrate; the first group III nitride single crystal is represented by a composition formula of AlAGaBInCN; and the layer of the second group III nitride single crystal is to be grown on the layer of the first group III nitride single crystal.
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公开(公告)号:US09859457B2
公开(公告)日:2018-01-02
申请号:US14715177
申请日:2015-05-18
Applicant: Nitek, Inc.
Inventor: Vinod Adivarahan , Asif Khan , Iftikhar Ahmad , Bin Zhang , Alexander Lunev
CPC classification number: H01L33/0075 , H01L21/02389 , H01L21/0242 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/02639 , H01L21/02647 , H01L33/22 , H01L33/32
Abstract: A template for a semiconductor device is made by providing an AGN substrate, growing a first layer of Group III nitrides on the substrate, depositing a thin metal layer on the first layer, annealing the metal such as gold so that it agglomerates to form a pattern of islands on the first layer; transferring the pattern into the first layer by etching then removing excess metal; and then depositing a second Group III nitride layer on the first layer. The second layer, through lateral overgrowth, coalesces over the gaps in the island pattern leaving a smooth surface with low defect density. A Group III semiconductor device may then be grown on the template, which may then be removed. Chlorine gas may be used for etching the pattern in the first layer and the remaining gold removed with aqua regia.
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公开(公告)号:US20170352721A1
公开(公告)日:2017-12-07
申请号:US15681971
申请日:2017-08-21
Applicant: MITSUBISHI CHEMICAL CORPORATION
Inventor: Kenji ISO , Hiromitsu KIMURA , Yuya SAITO , Yuuki ENATSU
CPC classification number: H01L29/045 , C23C16/34 , C30B25/04 , C30B29/406 , H01L21/02389 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/02516 , H01L21/0254 , H01L21/02576 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L29/0603 , H01L29/2003
Abstract: A C-plane GaN substrate only mildly restricts the shape and dimension of a nitride semiconductor device formed on the substrate. The variation of an off-angle on the main surface of the substrate is suppressed. In the C-plane GaN substrate: the substrate comprises a plurality of facet growth areas each having a closed ring outline-shape on the main surface; the number density of the facet growth area accompanied by a core among the plurality of facet growth areas is less than 5 cm−2 on the main surface; and, when any circular area of 4 cm diameter is selected from an area which is on the main surface and is distant by 5 mm or more from the outer peripheral edge of the substrate, the variation widths of an a-axis direction component and an m-axis direction component of an off-angle within the circular area is each 0.25 degrees or less.
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38.
公开(公告)号:US20170335488A1
公开(公告)日:2017-11-23
申请号:US15589016
申请日:2017-05-08
Inventor: MASAKI FUJIKANE
CPC classification number: C30B29/406 , B01D53/261 , C30B33/005 , C30B33/04 , C30B33/08 , C30B33/12 , E03B3/28 , H01L21/02389 , H01L21/0243 , H01L21/0254 , H01L21/02664
Abstract: A device includes a semiconductor substrate containing gallium nitride and having a crystal face inclined from 0.05° to 15° inclusive with respect to the c-plane. The semiconductor substrate includes an irregular portion on the crystal face, and the contact angle of pure water having a specific resistance of 18 MΩ·cm or more on the surface of the irregular portion is 10° or less.
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39.
公开(公告)号:US09748410B2
公开(公告)日:2017-08-29
申请号:US15028033
申请日:2014-10-15
Applicant: Tokuyama Corporation
Inventor: Toru Kinoshita , Toshiyuki Obata , Toru Nagashima
IPC: H01L29/00 , H01L29/872 , H01L29/47 , H01L29/36 , H01L29/66 , H01L29/20 , H01L29/207 , H01L21/02 , C30B25/20 , C30B29/40 , H01L29/32 , H01L29/04 , H01L29/205
CPC classification number: H01L29/872 , C30B25/20 , C30B29/403 , H01L21/02389 , H01L21/0254 , H01L21/02576 , H01L21/02598 , H01L21/0262 , H01L29/04 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/32 , H01L29/36 , H01L29/47 , H01L29/66143
Abstract: A vertical nitride semiconductor device includes an n-type aluminum nitride single-crystal substrate having an Si content of 3×1017 to 1×1020 cm−3 and a dislocation density of 106 cm−2 or less. An ohmic electrode layer is formed on an N-polarity side of the n-type aluminum nitride single-crystal substrate.
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公开(公告)号:US09721792B2
公开(公告)日:2017-08-01
申请号:US14465330
申请日:2014-08-21
Applicant: Applied Materials, Inc.
Inventor: Yi-Chiau Huang , Yihwan Kim
CPC classification number: H01L21/02587 , H01L21/0237 , H01L21/02373 , H01L21/02378 , H01L21/02389 , H01L21/02439 , H01L21/0245 , H01L21/02502 , H01L21/02521 , H01L21/02524 , H01L21/02529 , H01L21/02532 , H01L21/02538 , H01L21/0254 , H01L21/02554 , H01L21/02617 , H01L21/0262 , H01L21/02664 , H01L21/67115
Abstract: Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects.
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