公开(公告)号：US09214579B2

公开(公告)日：2015-12-15

申请号：US14534684

申请日：2014-11-06

Applicant: XINTEC INC.

Inventor： Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/0232 ,  H01L31/02 ,  H01L31/18 ,  H01L31/0236

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了具有硅衬底和保护层的晶片结构。 保护层上的电焊盘通过硅衬底的凹入区露出。 在硅基板的侧壁上形成隔离层，该隔离层包围该凹陷区域以及该硅基板的远离该保护层的表面。 在隔离层和电焊盘上形成再分布层。 在再分布层上形成钝化层。 图案化钝化层以在其中形成第一开口。 在通过第一开口露出的再分布层上形成第一导电层。 导电结构布置在第一开口中，使得导电结构与第一导电层电接触。

公开(公告)号：US09209124B2

公开(公告)日：2015-12-08

申请号：US13964999

申请日：2013-08-12

Applicant: XINTEC INC.

Inventor： Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/58 ,  H01L23/525 ,  H01L29/06 ,  H01L21/683

CPC classification number: H01L23/585 ,  H01L21/283 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/525 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/1302 ,  H01L2224/131 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括具有第一表面和与其相对的第二表面的半导体衬底。 导电垫位于第一表面上。 侧凹部位于半导体衬底的至少第一侧上，其中侧凹部从第一表面朝向第二表面延伸并跨越第一侧的整个长度。 导电层位于第一表面上并电连接到导电焊盘，其中导电层延伸到侧凹槽。

公开(公告)号：US20150340330A1

公开(公告)日：2015-11-26

申请号：US14715445

申请日：2015-05-18

Applicant: XINTEC INC.

Inventor： Geng-Peng PAN ,  Yi-Ming CHANG ,  Chia-Sheng LIN

IPC: H01L23/00 ,  H01L21/033 ,  H01L21/302 ,  H01L23/48 ,  H01L21/268

CPC classification number: H01L24/03 ,  H01L21/0273 ,  H01L21/0334 ,  H01L21/268 ,  H01L21/302 ,  H01L21/48 ,  H01L21/481 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03831 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2924/00014

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.

Abstract translation: 半导体结构的制造方法包括以下步骤。 在晶片衬底的第一表面上形成第一隔离层。 导电焊盘形成在第一隔离层上。 形成穿过第一表面的中空区域和晶片衬底的第二表面，使得第一隔离层通过中空区域露出。 对通过中空区域暴露的第一隔离层进行激光蚀刻处理，使得在第一隔离层中形成第一开口，并且在导电焊盘中形成通过第一开口暴露的凹部。

公开(公告)号：US20150325551A1

公开(公告)日：2015-11-12

申请号：US14706892

申请日：2015-05-07

Applicant: XINTEC INC.

Inventor： Ying-Nan WEN ,  Chien-Hung LIU

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/94 ,  B81B7/007 ,  B81B2207/012 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48149 ,  H01L2224/48451 ,  H01L2224/48464 ,  H01L2225/06506 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided.

公开(公告)号：US09177862B2

公开(公告)日：2015-11-03

申请号：US13727976

申请日：2012-12-27

Applicant: Xintec Inc.

Inventor： Yen-Shih Ho ,  Hsin Kuan ,  Long-Sheng Yeou ,  Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L21/56 ,  H01L23/498 ,  H01L21/78 ,  H01L23/48 ,  H01L23/28 ,  H01L21/82 ,  H01L23/14 ,  H01L21/683 ,  H01L21/768 ,  B81B7/00 ,  H01L23/00

CPC classification number: H01L21/82 ,  B81B7/007 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/14 ,  H01L23/147 ,  H01L24/08 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/80006 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/1461 ,  H01L2224/82 ,  H01L2224/80 ,  H01L21/78

Abstract: A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products.

Abstract translation: 半导体堆叠结构的制造方法主要包括：将第一规格的晶片分割成多个芯片; 将芯片重新排列成晶片的第二规格，以通过多个块将芯片堆叠在第二规格的基板上; 在芯片上形成再分配层; 并执行切割处理以获得多个半导体堆叠结构。 因此，本发明允许通过使用常规设备来处理新规格的晶片，而不需要新的工厂建筑物或设备。 因此，可以及时提供芯片封装以满足电子产品的更换速度。

公开(公告)号：US20150311175A1

公开(公告)日：2015-10-29

申请号：US14697235

申请日：2015-04-27

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Chih-Wei HO ,  Tsang-Yu LIU

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L23/49811 ,  B81B7/007 ,  B81B2207/093 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L2224/06165 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/4801 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81469 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/19107 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/85 ,  H01L2224/45099

Abstract: A stacked chip package is provided. The stacked chip package includes a first substrate having a first side and a second side opposite thereto. The first substrate includes a recess therein. The recess adjoins a side edge of the first substrate. A plurality of redistribution layers is disposed on the first substrate and extends onto the bottom of the recess. A second substrate is disposed on the first side of the first substrate. A plurality of bonding wires is correspondingly disposed on the redistribution layers in the recess, and extends onto the second substrate. A device substrate is disposed on the second side of the first substrate. A method of forming the stacked chip package is also provided.

Abstract translation: 提供堆叠的芯片封装。 堆叠的芯片封装包括具有第一侧和与其相对的第二侧的第一基板。 第一基板在其中包括凹部。 所述凹部邻接所述第一基板的侧边缘。 多个再分配层设置在第一基板上并延伸到凹部的底部。 第二基板设置在第一基板的第一侧上。 多个接合线相应地设置在凹部中的再分配层上并且延伸到第二基板上。 器件衬底设置在第一衬底的第二侧上。 还提供了形成堆叠芯片封装的方法。

公开(公告)号：US20150295097A1

公开(公告)日：2015-10-15

申请号：US14682888

申请日：2015-04-09

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Shu-Ming CHANG ,  Po-Han LEE

IPC: H01L31/0203 ,  H01L31/02 ,  H01L31/18

CPC classification number: H01L31/0203 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/13 ,  H01L31/02005 ,  H01L31/18 ,  H01L2224/131 ,  H01L2224/73253 ,  Y02P70/521 ,  H01L2924/014

Abstract: A chip package includes semiconductor chips, inner spacers, cavities, conductive portions and solder balls. The semiconductor chip has at least an electronic component and at least an electrically conductive pad disposed on an upper surface thereof. The conductive pad is arranged abreast to one side of the electronic component and electrically connected thereto. The cavities open to a lower surface of the semiconductor chip and extend toward the upper surface to expose the conductive pad on the upper surface. The conductive portions fill the cavities from the lower surface and electrically connected the to conductive pad. The solder balls are disposed on the lower surface and electrically connected to the conductive portions. A gap is created between an outer wall of the inner spacers and an edge of the semiconductor chip.

Abstract translation: 芯片封装包括半导体芯片，内部间隔件，空腔，导电部分和焊球。 半导体芯片至少具有电子部件，并且至少设置在其上表面上的导电焊盘。 导电焊盘与电子部件的一侧并排设置并与之电连接。 空腔通向半导体芯片的下表面并朝向上表面延伸以暴露上表面上的导电焊盘。 导电部分从下表面填充空腔并电连接到导电垫。 焊球设置在下表面上并电连接到导电部分。 在内隔板的外壁和半导体芯片的边缘之间产生间隙。

公开(公告)号：US09153707B2

公开(公告)日：2015-10-06

申请号：US13912792

申请日：2013-06-07

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Ying-Nan Wen ,  Tsang-Yu Liu

IPC: H01L31/0232 ,  H01L31/02 ,  H01L27/146

CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L31/02002 ,  H01L31/0232 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 设置在所述半导体衬底中的器件区域; 设置在所述半导体衬底的第一表面上的电介质层; 布置在所述电介质层中并电连接到所述器件区的导电焊盘结构，设置在所述电介质层上的载体衬底; 以及设置在所述载体基板的底表面中并与所述导电焊盘结构电接触的导电结构。

公开(公告)号：US20150279900A1

公开(公告)日：2015-10-01

申请号：US14613231

申请日：2015-02-03

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/11

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A carrier and a dam element are provided, and the dam element is adhered to the carrier by a temporary bonding layer. The dam element is bonded on the wafer. A first isolation layer, a redistribution layer, a second isolation layer, and a conductive structure are formed on the wafer in sequence. The carrier, the dam element and the wafer are diced to form a semiconductor element. The semiconductor element is disposed on a printed circuit board, such that the conductive structure is electrically connected to the printed circuit board. An adhesion force of the temporary bonding layer is eliminated to remove the carrier. A lens assembly is disposed on the printed circuit board, such that the semiconductor element without the carrier is located in the lens assembly.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了载体和坝元件，并且坝元件通过临时粘合层粘附到载体上。 坝体结合在晶片上。 在晶片上依次形成第一隔离层，再分配层，第二隔离层和导电结构。 将载体，坝元件和晶片切割成半导体元件。 半导体元件设置在印刷电路板上，使得导电结构电连接到印刷电路板。 消除了临时粘合层的粘合力以除去载体。 透镜组件设置在印刷电路板上，使得没有载体的半导体元件位于透镜组件中。

公开(公告)号：US20150270236A1

公开(公告)日：2015-09-24

申请号：US14662151

申请日：2015-03-18

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Chia-Ming CHENG ,  Shu-Ming CHANG

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L29/0657 ,  H01L2224/02233 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/14155 ,  H01L2224/14165 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/00014

Abstract: The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at least one protrusion. The semiconductor chip has a plurality of conductive pads disposed on an upper surface of the semiconductor chip. The recess extends from the upper surface to a lower surface of the semiconductor chip, and is arranged on the side of the semiconductor chip. The first redistribution metal lines are disposed on the upper surface, electrically connected to the conductive pad individually, and extended into the recesses separately. The protrusion is disposed in the recess and located between the adjacent first redistribution metal lines.

Abstract translation: 本发明提供了一种芯片封装，其包括半导体芯片，至少一个凹槽，多个第一再分布金属线以及至少一个突起。 半导体芯片具有设置在半导体芯片的上表面上的多个导电焊盘。 凹部从半导体芯片的上表面延伸到下表面，并且布置在半导体芯片的侧面上。 第一再分布金属线设置在上表面上，分别电连接到导电垫，并分别延伸到凹槽中。 突出部设置在凹部中并且位于相邻的第一再分布金属线之间。