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公开(公告)号：US06689543B2
公开(公告)日：2004-02-10
申请号：US10073558
申请日：2002-02-11
IPC分类号： G03C556
CPC分类号： H05K3/0032 , B23K2103/42 , B23K2103/50 , B41M5/24 , H05K1/0326 , H05K1/0373 , H05K2201/0112 , Y10S430/146
摘要： An epoxy based resin which exhibits good laser ablation and good adherence to a substrate such a copper is provided by adding to the resin a dye or dyes having substantial energy absorption at the emission wave lengths of lasers used to laser ablate the resin. The resin with the dye or dyes included is coated onto a substrate and cured, or laminated onto a substrate in the cured condition. The required openings are formed in the cured film by laser ablation. This allows for the use of optimum techniques to be used to form micro vias.
摘要翻译： 通过向树脂中添加染料或染料，在用于激光烧蚀树脂的激光器的发射波长处具有显着的能量吸收，提供了表现出良好的激光烧蚀和对衬底的良好粘合性的环氧树脂。 将含有染料或染料的树脂涂覆在基材上并固化，或在固化条件下层压到基材上。 通过激光烧蚀在所述固化膜中形成所需的开口。 这允许使用最佳技术来形成微通孔。
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公开(公告)号：US06427323B2
公开(公告)日：2002-08-06
申请号：US09859690
申请日：2001-05-17
IPC分类号： H05K336
CPC分类号： H05K3/325 , H05K3/4614 , H05K2201/0373 , H05K2201/09536 , H05K2201/10666 , Y10T29/49126 , Y10T29/49128 , Y10T29/49165 , Y10T29/49194
摘要： A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.”
摘要翻译： 提供了一种用于连接电子电路封装中的两个导电层的方法，包括以下步骤：在第一导电层的选定区域上形成枝晶，在第二导电层的选定区域上形成枝晶，在第一导电层上施加环氧粘合剂材料 并且将第二导电层压缩附接到第一导电层，使得第一导电层上的枝晶与第二导电层上的枝晶接触。 还要求保护的是包括用于根据本发明制造的电互连的树突的电子电路封装。 本发明的替代实施例利用具有树突的中间表面金属代替“通孔”。
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公开(公告)号：US06426466B1
公开(公告)日：2002-07-30
申请号：US09501480
申请日：2000-02-09
IPC分类号： H05K102
CPC分类号： H05K1/0263 , H01R12/7088 , H05K3/325 , H05K3/403 , H05K3/4641 , H05K2201/0919 , H05K2201/10272 , H05K2201/2018
摘要： A printed wiring board structure having peripheral power input. A printed wiring board having internal conductive layers, wherein each internal conductive layer contains a plurality of tabs extending therefrom. Tabs of similar voltage are vertically aligned within the printed wiring board. A frame within which the printed wiring board is mounted is also provided. The frame, having connections mounted within an inner surface of the frame, electrically contacts the tabs along the periphery of the printed wiring board.
摘要翻译： 具有外围电源输入的印刷电路板结构。 一种具有内部导电层的印刷线路板，其中每个内部导电层包含从其延伸的多个翼片。 类似电压的标签在印刷电路板内垂直对齐。 还提供了安装印刷电路板的框架。 具有安装在框架的内表面内的连接的框架沿着印刷线路板的周边与接片电接触。
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公开(公告)号：US06423905B1
公开(公告)日：2002-07-23
申请号：US09562109
申请日：2000-05-01
IPC分类号： H05K103
CPC分类号： H05K3/4688 , H05K1/0271 , H05K3/429 , H05K2201/0133 , H05K2201/0195
摘要： A printed wiring board having a layered composite of metal planes and dielectric layers. At least one of the dielectric layers has a modulus lower than the modulus of the remaining dielectric material layers. A plating, extending through the layered composite, has a first land on a first external surface of the layered composite, a second land on a second external surface of the layered composite, and a barrel extending between the first land and the second land. The lower modulus dielectric material layer deforms during thermal excursions of the printed wiring board in such a way as to reduce the strains imposed on both the lands and the barrel of the plated through holes.
摘要翻译： 一种具有金属平面和电介质层的复合层的印刷电路板。 电介质层中的至少一个具有低于剩余介电材料层的模量的模量。 延伸穿过层状复合材料的电镀具有在层状复合材料的第一外表面上的第一焊盘，层状复合材料的第二外表面上的第二焊盘，以及在第一焊盘和第二焊盘之间延伸的镜筒。 在印刷线路板的热偏移期间，较低模量的介电材料层变形，以便减小施加在电镀通孔的焊盘和圆筒上的应变。
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公开(公告)号：US06361923B1
公开(公告)日：2002-03-26
申请号：US09375957
申请日：1999-08-17
IPC分类号： G03C173
CPC分类号： H05K3/0032 , B23K2103/42 , B23K2103/50 , B41M5/24 , H05K1/0326 , H05K1/0373 , H05K2201/0112 , Y10S430/146
摘要： An epoxy based resin which exhibits good laser ablation and good adherence to a substrate such a copper is provided by adding to the resin a dye or dyes having substantial energy absorption at the emission wave lengths of lasers used to laser ablate the resin. The resin with the dye or dyes included is coated onto a substrate and cured, or laminated onto a substrate in the cured condition. The required openings are formed in the cured film by laser ablation. This allows for the use of optimum techniques to be used to form micro vias.
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公开(公告)号：US06204456B1
公开(公告)日：2001-03-20
申请号：US09159938
申请日：1998-09-24
IPC分类号： H01R909
CPC分类号： H05K3/0094 , H01R12/523 , H05K3/0023 , H05K3/4602 , H05K2201/0209 , H05K2201/09536 , H05K2201/0959 , Y10T29/49165
摘要： Methods of filling apertures, for example, through holes, in substrates are provided. The methods utilize a dielectric film, preferably a photoimageable dielectric film, which is employed to fill the apertures and to form a dielectric film disposed above the substrate at the same time. As a result, the aperture fill material is the same as, and indeed continuous with, the dielectric film which is disposed on the substrate. The method employs the following steps: providing a substrate having apertures; providing a dielectric film disposed on the substrate covering the apertures, reflowing the dielectric film to flow into the apertures and to form a dielectric film adherent to the substrate, to provide a continuous dielectric extending from the dielectric film into the apertures. In certain embodiments, after filling, additional apertures, such as vias, are photoimaged in the dielectric film. Preferably the vias are then metallized, and circuitry formed atop the dielectric film.
摘要翻译： 提供了在基板中填充孔的方法，例如通孔。 该方法利用电介质膜，优选可光成像的介电膜，其用于填充孔并同时形成设置在基板上方的电介质膜。 结果，孔填充材料与设置在基底上的电介质膜相同，实际上是连续的。 该方法采用以下步骤：提供具有孔的基底; 提供设置在覆盖所述孔的基板上的电介质膜，回流所述电介质膜流入所述孔中并形成与所述衬底粘附的电介质膜，以提供从所述电介质膜延伸到所述孔中的连续电介质。 在某些实施例中，在填充之后，附加的孔，例如通孔，在电介质膜中被光刻。 优选地，将通孔金属化，并且在电介质膜的顶部形成电路。
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公开(公告)号：US6009619A
公开(公告)日：2000-01-04
申请号：US864632
申请日：1997-05-28
申请人： John M. Lauffer
发明人： John M. Lauffer
CPC分类号： H05K1/112 , H05K3/0023 , H05K3/225 , H05K3/3442 , H05K3/4652 , H05K1/0292 , H05K2201/0305 , H05K2201/0355 , H05K2201/09472 , H05K2201/10636 , H05K2203/0551 , H05K3/3452 , H05K3/4038 , Y02P70/611 , Y02P70/613 , Y10T29/49144 , Y10T29/49146 , Y10T29/49149 , Y10T29/49156
摘要： An electronic circuit card and a process of manufacturing the electronic circuit card. The process includes the steps of providing the electronic circuit card with external electrical circuits. A photoimageable dielectric layer is formed on the electronic circuit card. A metal foil layer is laminated on the photoimageable dielectric layer and the metal foil layer is patterned to form a wire and a component add land pattern. The photoimageable dielectric layer is patterned and the wire and the component add land pattern are electrically connected to the electronic circuit card.
摘要翻译： 一种电子电路卡及其制造方法。 该过程包括为电子电路卡提供外部电路的步骤。 在电子电路卡上形成可光成像的电介质层。 在可光成像的介电层上层压金属箔层，对金属箔层进行图案化以形成导线和添加焊盘图案的部件。 将可光成像的介质层图案化，并将导线和部件添加焊盘图案电连接到电子电路卡。
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公开(公告)号：US5977642A
公开(公告)日：1999-11-02
申请号：US918085
申请日：1997-08-25
IPC分类号： H01L21/48 , H01L21/56 , H01L21/60 , H01L23/498 , H05K3/32 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/81 , H01L21/4853 , H01L21/563 , H01L23/49811 , H05K3/325 , H01L2224/13144 , H01L2224/16225 , H01L2224/73203 , H01L2224/81801 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H05K2201/10734 , H05K2201/10977 , H05K2203/0307 , H05K2203/0723 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155
摘要： A method is provided for connecting two conductive surfaces in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive surface, applying a dielectric insulation material over the first conductive surface such that the dendrites are exposed through the insulation material to leave a substantially planar surface of exposed dendrites, and placing a second conductive surface on top of the exposed dendrites. The second conductive surface may be a surface metal, a chip bump array, or a ball grid array. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection and planarization manufactured in accordance with the present invention.
摘要翻译： 提供了一种用于连接电子电路封装中的两个导电表面的方法，包括以下步骤：在第一导电表面的选定区域上形成枝晶，在第一导电表面上施加介电绝缘材料，使得枝晶通过绝缘材料暴露于 留下暴露的树突的基本上平坦的表面，并将第二导电表面放置在暴露的树突上。 第二导电表面可以是表面金属，芯片凸块阵列或球栅阵列。 还要求保护的是包含用于根据本发明制造的电互连和平坦化的树突的电子电路封装。
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69.发明授权Via fill compositions for direct attach of devices and methods for applying same 失效用于直接连接装置的填充组合物和用于施加装置的方法
公开(公告)号：US5571593A
公开(公告)日：1996-11-05
申请号：US467558
申请日：1995-06-06
申请人： Roy L. Arldt , Christina M. Boyko , Burtran J. Cayson , Richard M. Kozlowski , Joseph D. Kulesza , John M. Lauffer , Philip C. Liu , Voya R. Markovich , Issa S. Mahmoud , James F. Muska , Kostas Papathomas , Joseph G. Sabia , Richard A. Schumacher
发明人： Roy L. Arldt , Christina M. Boyko , Burtran J. Cayson , Richard M. Kozlowski , Joseph D. Kulesza , John M. Lauffer , Philip C. Liu , Voya R. Markovich , Issa S. Mahmoud , James F. Muska , Kostas Papathomas , Joseph G. Sabia , Richard A. Schumacher
IPC分类号： B32B7/04 , C08G59/40 , C08G73/00 , C08L63/00 , C09D163/00 , H01B1/20 , H01B1/22 , H01B1/24 , H05K1/09 , H05K1/11 , H05K1/16 , H05K3/00 , H05K3/40 , B32B9/00
CPC分类号： H01B1/24 , B32B7/04 , H01B1/22 , H05K1/095 , H05K1/113 , H05K1/167 , H05K3/4053 , H05K3/4069 , H01L2224/16235 , H05K1/16 , H05K2201/0347 , H05K2201/09563 , H05K2201/10734 , H05K2203/0126 , H05K2203/0191 , H05K2203/0207 , H05K2203/0278 , H05K2203/0338 , H05K2203/0763 , H05K3/0023 , H05K3/0047 , H05K3/0094 , Y10S428/901 , Y10T29/49099 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T428/24273 , Y10T428/24331 , Y10T428/24339 , Y10T428/24826 , Y10T428/24917 , Y10T428/24926 , Y10T428/25
摘要： The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.
摘要翻译： 本发明允许焊接接头直接制成通孔和通孔，而不会通过用环氧树脂或氰酸盐填充组合物填充电镀通孔，焊料不会被弄脏到通孔或通孔中。 当固化和过度镀覆时，填充组合物为焊接接头提供支撑，并为相互连接提供平坦的可焊接表面。 在某些实施方案中，固化的填充组合物提供另外的导电性的优点。 本发明还涉及用这种填充组合物填充通孔的几种新方法，以及位于通孔和通孔中的电阻器。
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70.发明授权公开(公告)号：US09451693B2
公开(公告)日：2016-09-20
申请号：US13198756
申请日：2011-08-05
申请人： Rabindra N. Das , Voya R. Markovich , John M. Lauffer , Roy H. Magnuson , Konstantinos I. Papathomas , Benson Chan
发明人： Rabindra N. Das , Voya R. Markovich , John M. Lauffer , Roy H. Magnuson , Konstantinos I. Papathomas , Benson Chan
CPC分类号： H05K1/0313 , B23K26/382 , B23K26/40 , B23K2101/40 , B23K2103/16 , B23K2103/172 , B23K2103/52 , H01B1/22 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/01322 , H01L2924/15311 , H05K1/097 , H05K3/4053 , H05K3/4069 , H05K3/462 , H05K3/4623 , H05K3/4641 , H05K2201/0257 , H05K2201/09536 , H05K2201/0959 , H05K2201/096 , H05K2201/09718 , H05K2201/10378 , H05K2203/0425 , H05K2203/1152 , Y10T29/49128 , Y10T29/49165 , H01L2924/00
摘要： A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.
摘要翻译： 用于连接多级Z轴互连的多层导电粘合剂（ECA）混合物和形成连接多级Z轴互连的ECA的方法。 具有多层能力的ECA包含允许糊料适应特定要求的组成成分的混合物，其中制造电路化衬底组件的方法，其中具有潜在不同的热膨胀系数（CTE）的两个或更多个子组件对齐，并且Z- 在连接期间创建轴互连。 导体的冶金和多层导电浆料的冶金被有效地混合，并且在配合子组件之间使用的可流动的中间电介质流动以接合和围绕导体耦合。
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