公开(公告)号：US08629557B2

公开(公告)日：2014-01-14

申请号：US13414877

申请日：2012-03-08

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/48 ,  H01L21/00 ,  B23K31/00

CPC classification number: H01L22/30 ,  H01L22/12 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05584 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13028 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.

Abstract translation: 用于检测基座侧壁焊料润湿的结构和方法。 该结构包括具有集成电路芯片阵列的半导体晶片，每个集成电路芯片具有芯片基座阵列，其具有位于芯片基座顶部的相应的芯片焊料柱，基座沿第一方向隔开第一距离;以及 在垂直于第一方向的第二方向上间隔开的第二距离; 以及设置在所述晶片与所述集成电路芯片的不同区域中的至少一个监视器结构，所述监视器结构至少包括在所述第一基座的顶表面上的第一基座和第一焊料柱，以及第二基座和第二焊接柱 在第二基座的顶表面上，第一和第二基座间隔第三距离，第三距离小于第一和第二距离。

公开(公告)号：US20130234316A1

公开(公告)日：2013-09-12

申请号：US13415902

申请日：2012-03-09

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/31144 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/0381 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/14104 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: The invention provides a semiconductor chip structure having at least one aluminum pad structure and a polyimide buffering layer under the aluminum pad structure, wherein the polyimide buffering layer is self-aligned to the aluminum pad structure, and a method of forming the same. The method includes forming a polyimide buffering layer on a substrate, forming an aluminum pad structure on the buffering layer, and, using the aluminum pad structure as a mask, etching the substrate to remove the polyimide buffering layer from the substrate everywhere except under the aluminum pad structure.

Abstract translation: 本发明提供一种半导体芯片结构，其具有在铝焊盘结构下方的至少一个铝焊盘结构和聚酰亚胺缓冲层，其中聚酰亚胺缓冲层与铝焊盘结构自对准，以及其形成方法。 该方法包括在基板上形成聚酰亚胺缓冲层，在缓冲层上形成铝焊盘结构，并且使用铝焊盘结构作为掩模，蚀刻基板以除去铝以外的其他处理的基板 垫结构。

公开(公告)号：US08426247B2

公开(公告)日：2013-04-23

申请号：US13463855

申请日：2012-05-04

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L21/44

CPC classification number: H01L23/49816 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/11822 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/17051 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10674 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A method of connecting chips to chip carriers, ceramic packages, etc. (package substrates) forms smaller than usual first solder balls and polymer pillars on the surface of a semiconductor chip and applies adhesive to the distal ends of the polymer pillars. The method also forms second solder balls, which are similar in size to the first solder balls, on the corresponding surface of the package substrate to which the chip will be attached. Then, the method positions the surface of the semiconductor chip next to the corresponding surface of the package substrate. The adhesive bonds the distal ends of the polymer pillars to the corresponding surface of the package substrate. The method heats the first solder balls and the second solder balls to join the first solder balls and the second solder balls into solder pillars.

Abstract translation: 将芯片与芯片载体，陶瓷封装等（封装基板）连接的方法比半导体芯片表面上的通常的第一焊球和聚合物柱形成的小，并且将粘合剂施加到聚合物柱的远端。 该方法还形成与芯片将附接到的封装衬底的相应表面上尺寸相似的第二焊球。 然后，该方法将半导体芯片的表面定位在封装衬底的相应表面的旁边。 粘合剂将聚合物柱的末端粘合到包装基底的相应表面上。 该方法加热第一焊球和第二焊球以将第一焊球和第二焊球接合成焊料柱。

公开(公告)号：US08350383B2

公开(公告)日：2013-01-08

申请号：US12503870

申请日：2009-07-16

Applicant: Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/04

CPC classification number: H01L23/49816 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01067 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An IC chip package, in one embodiment, may include an IC chip including an upper surface including an overhang extending beyond a sidewall of the IC chip, and underfill material about the sidewall and under the overhang. The overhang prevents underfill material from extending over an upper surface of the IC chip. In another embodiment, a ball grid array (BGA) is first mounted to landing pads on a lower of two joined IC chip packages. Since the BGA is formed on the lower IC chip package first, the BGA acts as a dam for the underfill material thereon. The underfill material extends about the respective IC chip and surrounds a bottom portion of a plurality of solder elements of the BGA and at least a portion of respective landing pads thereof.

Abstract translation: 在一个实施例中，IC芯片封装可以包括IC芯片，其包括包括延伸超过IC芯片的侧壁的突出部分的上表面，以及围绕侧壁和突出部分下方的底部填充材料。 悬垂防止底部填充材料在IC芯片的上表面上延伸。 在另一个实施例中，首先将球栅阵列（BGA）安装到两个连接的IC芯片封装的较低的焊盘上。 由于BGA首先形成在下部IC芯片封装上，所以BGA用作其上的底部填充材料的坝。 底部填充材料围绕相应的IC芯片延伸并围绕BGA的多个焊料元件的底部以及其各自的着陆焊盘的至少一部分。

公开(公告)号：US08338947B2

公开(公告)日：2012-12-25

申请号：US13361232

申请日：2012-01-30

Applicant: Timothy H. Daubenspeck ,  Timothy D. Sullivan

Inventor： Timothy H. Daubenspeck ,  Timothy D. Sullivan

IPC: H01L23/498

CPC classification number: H01L23/488 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/13007 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45147 ,  H01L2224/48824 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad.

公开(公告)号：US20120313215A1

公开(公告)日：2012-12-13

申请号：US13588218

申请日：2012-08-17

Applicant: Joseph M. LUKAITIS ,  Jed H. RANKIN ,  Robert R. ROBISON ,  Dustin K. SLISHER ,  Timothy D. SULLIVAN

Inventor： Joseph M. LUKAITIS ,  Jed H. RANKIN ,  Robert R. ROBISON ,  Dustin K. SLISHER ,  Timothy D. SULLIVAN

IPC: H01L29/02 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L28/20

Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.

Abstract translation: 形成半导体结构的方法包括在衬底上的绝缘体层上形成电阻器，并且在电阻器上方形成至少一个电介质层。 所述方法还包括通过所述至少一个电介质层，通过所述电阻器，穿过所述绝缘体层，并进入所述衬底形成衬底接触。 衬底接触包括高导热性材料。

公开(公告)号：US08298904B2

公开(公告)日：2012-10-30

申请号：US13008465

申请日：2011-01-18

Applicant: Joseph M. Lukaitis ,  Jed H. Rankin ,  Robert R. Robison ,  Dustin K. Slisher ,  Timothy D. Sullivan

Inventor： Joseph M. Lukaitis ,  Jed H. Rankin ,  Robert R. Robison ,  Dustin K. Slisher ,  Timothy D. Sullivan

IPC: H01L21/20

CPC classification number: H01L27/1203 ,  H01L28/20

Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.

Abstract translation: 形成半导体结构的方法包括在衬底上的绝缘体层上形成电阻器，并且在电阻器上方形成至少一个电介质层。 所述方法还包括通过所述至少一个电介质层，通过所述电阻器，穿过所述绝缘体层，并进入所述衬底形成衬底接触。 衬底接触包括高导热性材料。

公开(公告)号：US20120187558A1

公开(公告)日：2012-07-26

申请号：US13433974

申请日：2012-03-29

Applicant: Charles L. ARVIN ,  Raschid J. BEZAMA ,  Harry D. COX ,  Timothy H. DAUBENSPECK ,  Krystyna W. SEMKOW ,  Timothy D. SULLIVAN

Inventor： Charles L. ARVIN ,  Raschid J. BEZAMA ,  Harry D. COX ,  Timothy H. DAUBENSPECK ,  Krystyna W. SEMKOW ,  Timothy D. SULLIVAN

IPC: H01L23/498

CPC classification number: H01L24/05 ,  C25D5/02 ,  C25D5/14 ,  C25D5/48 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05075 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/01027

Abstract: Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.

Abstract translation: 提供互连结构及其制造方法。 互连结构提供用于改善载流能力（例如，电流扩展）的高可靠性铜互连结构。 该结构包括在沟槽中形成的凸块下金属。 凸起下冶金至少包括：粘合层; 电镀阻挡层; 以及设置在粘合层和镀层阻挡层之间的镀覆导电金属层。 该结构还包括形成在凸块下金属上的焊料凸块。

公开(公告)号：US20120139123A1

公开(公告)日：2012-06-07

申请号：US12960110

申请日：2010-12-03

Applicant: Timothy H. Daubenspeck ,  Gary Lafontant ,  Ekta Misra ,  David L. Questad ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Thomas A. Wassick ,  Steven L. Wright

Inventor： Timothy H. Daubenspeck ,  Gary Lafontant ,  Ekta Misra ,  David L. Questad ,  George J. Scott ,  Krystyna W. Semkow ,  Timothy D. Sullivan ,  Thomas A. Wassick ,  Steven L. Wright

IPC: H01L23/52 ,  G06F17/50 ,  H01L21/44

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13006 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3511 ,  Y02P90/265 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.

Abstract translation: 提供半导体结构，制造方法和设计结构。 该结构包括与芯片的下面的金属焊盘接触形成的至少一个偏移月牙形焊料通孔。 至少一个偏移月牙形通孔相对于下面的金属焊盘和下面的金属层中的至少一个与芯片的与下面的金属层电接触的互连直接电接触而偏移。

公开(公告)号：US20120122260A1

公开(公告)日：2012-05-17

申请号：US13357728

申请日：2012-01-25

Applicant: Ethan H. Cannon ,  Michael J. Hauser ,  Timothy D. Sullivan

Inventor： Ethan H. Cannon ,  Michael J. Hauser ,  Timothy D. Sullivan

IPC: H01L31/18

CPC classification number: H01L31/115 ,  H01L23/552 ,  H01L23/556 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e.g., a microprocessor) to be protected from the adverse effects of the ionizing radiation particles. As such, the location where the radiation particles intersect the device layer can be calculated with coarse precision (e.g., to within 10 s of microns).

Abstract translation: 辐射传感器或检测器阵列集成在三维半导体IC内。 传感器阵列相对靠近电路（例如，微处理器）的器件层定位，以防止电离辐射粒子的不利影响。 因此，辐射粒子与器件层相交的位置可以用粗精度（例如，在10微米以内）来计算。