公开(公告)号：US09865548B2

公开(公告)日：2018-01-09

申请号：US15158963

申请日：2016-05-19

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Charles G. Woychik ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC: H01L21/00 ,  H01L23/49 ,  H01L21/76 ,  H01L23/532 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5328 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/83 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/014

Abstract: An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130) which is conductive and/or is coated with a conductive material (144). Such interconnects replace metal bond wires in some embodiments. Other features are also provided.

公开(公告)号：US09853004B2

公开(公告)日：2017-12-26

申请号：US15296286

申请日：2016-10-18

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

CPC classification number: H01L24/02 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L25/00 ,  H01L2224/02166 ,  H01L2224/02372 ,  H01L2224/05548 ,  H01L2224/11 ,  H01L2224/11011 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

公开(公告)号：US09741620B2

公开(公告)日：2017-08-22

申请号：US14749529

申请日：2015-06-24

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang ,  Hong Shen ,  Arkalgud R. Sitaram

IPC: H01L21/00 ,  H01L21/70 ,  H01L21/82 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L21/82 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L24/98 ,  H01L2224/04105 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

公开(公告)号：US09615451B2

公开(公告)日：2017-04-04

申请号：US14887674

申请日：2015-10-20

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H05K1/09 ,  H05K1/00 ,  H05K1/16 ,  H05K1/11 ,  H05K7/10 ,  H05K1/03 ,  H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H05K3/40 ,  H05K3/42

CPC classification number: H05K1/0306 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3731 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/09 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0323

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

公开(公告)号：US09607928B2

公开(公告)日：2017-03-28

申请号：US14729729

申请日：2015-06-03

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L21/4763 ,  H01L23/48 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/05647 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A component can include a substrate having an opening extending between first and second surfaces thereof, and an electrically conductive via having first and second portions. The first portion can include a first layer structure extending within the opening and at least partially along an inner wall of the opening, and a first principal conductor extending within the opening and at least partially overlying the first layer structure. The first portion can be exposed at the first surface and can have a lower surface located between the first and second surfaces. The second portion can include a second layer structure extending within the opening and at least partially along the lower surface of the first portion, and a second principal conductor extending within the opening and at least partially overlying the second layer structure. The second portion can be exposed at the second surface.

公开(公告)号：US09601398B2

公开(公告)日：2017-03-21

申请号：US14500858

申请日：2014-09-29

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Se Young Yang ,  Pezhman Monadgemi ,  Terrence Caskey ,  Cyprian Emeka Uzoh

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  G01R31/28 ,  H01L21/683 ,  H01L25/04 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L22/32 ,  G01R31/2886 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/04 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/11015 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/16257 ,  H01L2224/16267 ,  H01L2224/16503 ,  H01L2224/17051 ,  H01L2224/8109 ,  H01L2224/81138 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

公开(公告)号：US20170069599A1

公开(公告)日：2017-03-09

申请号：US14845150

申请日：2015-09-03

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L27/14634 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/09181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/−10 degrees.

Abstract translation: 在微电子封装中，第一引线接合线耦合到衬底的上表面。 第一接合块联接到第一引线接合线的另一端。 第二线接合线连接到上表面。 第二接合块联接到第二引线接合线的另一端。 第一和第二线接合线横向突出出离开衬底的上表面至少距离第一引线接合线和第二引线接合线的直径的大约2至3倍的距离。 第一引线接合线和第二引线接合线相对于上表面在+/- 10度内相互平行的距离是水平的。

公开(公告)号：US20170069575A1

公开(公告)日：2017-03-09

申请号：US15257152

申请日：2016-09-06

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Wael Zohni ,  Cyprian Emeka Uzoh

IPC: H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L25/10 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: A microelectronic assembly can be made by forming a redistribution structure supported on a carrier, the structure including two or more layers of deposited dielectric material and two or more electrically conductive layers and including conductive features such as pads and traces electrically interconnected by vias. Electrical connectors may project above a second surface of the structure opposite an interconnection surface of the redistribution structure adjacent to the carrier. A microelectronic element may be attached and electrically connected with conductive features at the second surface, and a dielectric encapsulation can be formed contacting the second surface and surfaces of the microelectronic element. Electrically conductive features at the interconnection surface can be configured for connection with corresponding features of a first external component, and the electrical connectors can be configured for connection with corresponding features of a second external component.

Abstract translation: 微电子组件可以通过形成负载在载体上的再分布结构来制造，该结构包括两层或更多层沉积的电介质材料和两个或更多个导电层，并且包括导电特征，例如通过通孔电连接的焊盘和迹线。 电连接器可以突出在结构的第二表面之上，与邻近载体的再分布结构的互连表面相对。 微电子元件可以在第二表面处附接并与导电特征电连接，并且可以形成接触微电子元件的第二表面和表面的电介质封装。 互连表面处的导电特征可以被配置为与第一外部部件的对应特征相连接，并且电连接器可被配置为与第二外部部件的对应特征相连接。

公开(公告)号：US09583426B2

公开(公告)日：2017-02-28

申请号：US14533728

申请日：2014-11-05

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Gabriel Z. Guevara ,  Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

Abstract translation: 插入器（110）在顶部和/或底部表面处具有用于连接到电路模块（例如IC 112）的接触焊盘。 插入器包括由多层（110.i）制成的衬底。 每个层可以是具有电路的衬底（110S），可能是陶瓷衬底。 基板垂直延伸。 在由对应于插入层的垂直层（310.i）制成的单个结构（310）中制造多个插入件。 沿着水平面（314）切割结构以提供插入件。 在切割之前和所有基板彼此附接之前，可以在基板表面上形成插入件的垂直导线（类似于贯穿基板通孔）。 因此，不需要对垂直导线进行贯通基板孔。 在基板彼此附接之前，也可以在基板表面上形成非垂直特征。 还提供了其他实施例。

公开(公告)号：US20170047307A1

公开(公告)日：2017-02-16

申请号：US15336192

申请日：2016-10-27

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05684 ,  H01L2224/11009 ,  H01L2224/11464 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13084 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13655 ,  H01L2224/13684 ,  H01L2224/13686 ,  H01L2224/13805 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13844 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16265 ,  H01L2224/16268 ,  H01L2224/16501 ,  H01L2224/2919 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81026 ,  H01L2224/81065 ,  H01L2224/81099 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/83026 ,  H01L2224/83815 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/3841 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Abstract translation: 制造组件的方法可以包括在第一衬底的第一表面处与第二衬底的主表面处的第二导电元件的顶表面并置第一导电元件的顶表面。 一个：第一导电元件的顶表面可以在第一表面下方凹入，或者第二导电元件的顶表面可以在主表面下方凹入。 导电纳米颗粒可以设置在第一和第二导电元件的顶表面之间。 导电纳米颗粒可以具有小于100纳米的长尺寸。 该方法还可以包括至少在并置的第一和第二导电元件的界面处升高温度至导电纳米颗粒可以在并置的第一和第二导电元件之间形成冶金接头的接合温度。