公开(公告)号：US20060202322A1

公开(公告)日：2006-09-14

申请号：US10564200

申请日：2004-09-22

Applicant: Takashi Kariya ,  Toshiki Furutani

Inventor： Takashi Kariya ,  Toshiki Furutani

IPC: H01L23/14 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K3/3436 ,  H05K3/4602 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An interposer capable of preventing breaking of a wiring pattern with an IC chip loaded on a package substrate. Stress due to a difference in thermal expansion coefficient between a multilayer printed wiring board having a large thermal expansion and the IC chip having a small thermal expansion can be absorbed by locating the interposer between the package substrate and the IC chip. Particularly by using an insulation substrate whose Young's modulus is 55 to 440 Gpa as the insulation substrate constituting the interposer, stress is absorbed within the interposer.

Abstract translation: 一种插入器，其能够防止在装载在封装基板上的IC芯片断开布线图案。 通过将封装基板和IC芯片之间的插入件定位，可以吸收由于热膨胀大的多层印刷布线板和热膨胀小的IC芯片之间的热膨胀系数的不同而产生的应力。 特别是通过使用杨氏模量为55〜440Gpa的绝缘基板作为构成中介层的绝缘基板，在内插器内吸收应力。

公开(公告)号：US20060137905A1

公开(公告)日：2006-06-29

申请号：US11356350

申请日：2006-02-17

Applicant: Takashi Kariya ,  Akira Mochida

Inventor： Takashi Kariya ,  Akira Mochida

IPC: H05K1/03

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10522 ,  H05K2201/10734

Abstract: A multilayer printed wiring board 10 includes: a mounting portion 60 on the top surface of which is mounted a semiconductor element that is electrically connected to a wiring pattern 32, etc.; and a capacitor portion 40 having a high dielectric constant layer 43, formed of ceramic and first and second layer electrodes 41 and 42 that sandwich the high dielectric constant layer 43. One of either of the first and second layer electrodes 41 and 42 is connected to a power supply line of the semiconductor element and the other of either of the first and second layer electrodes 41 and 42 is connected to a ground line. In this multilayer printed wiring board 10, high dielectric constant layer 43 included in the layered capacitor portion 40, which is connected between the power supply line and the ground line, is formed of ceramic. With this structure, the static capacitance of the layered capacitor portion 40 can be high, and an adequate decoupling effect is exhibited even under circumstances in which instantaneous potential drops occur readily.

Abstract translation: 多层印刷电路板10包括：安装部分60，其顶表面上安装有电连接到布线图案32的半导体元件; 以及具有由陶瓷形成的高介电常数层43的电容器部分40和夹在高介电常数层43上的第一和第二层电极41和42。第一和第二层电极41和42中的一个连接到 半导体元件的电源线和第一和第二层电极41和42中的另一个连接到接地线。 在这种多层印刷电路板10中，连接在电源线和接地线之间的层状电容器部分40中包括的高介电常数层43由陶瓷形成。 利用这种结构，层状电容器部分40的静态电容可以很高，并且即使在容易发生瞬时电位下降的情况下也可以发挥足够的去耦效应。

公开(公告)号：US06762921B1

公开(公告)日：2004-07-13

申请号：US09926476

申请日：2001-11-09

Applicant: Motoo Asai ,  Kouta Noda ,  Takashi Kariya

Inventor： Motoo Asai ,  Kouta Noda ,  Takashi Kariya

IPC: H02H322

CPC classification number: H05K3/4661 ,  H05K3/108 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/385 ,  H05K3/421 ,  H05K2201/0195 ,  H05K2201/09509 ,  Y10T428/24273

Abstract: This invention is to propose a technique of producing a printed wiring board having an excellent adhesion property between an electroless plated film and an electrolytic plated film constituting a conductor circuit through a semi-additive process without causing the peeling of a plating resist and is a printed wiring board comprising conductor circuits formed on a roughened surface of an insulating layer, in which the conductor circuit is constituted with an electroless plated film at the side of the insulating layer and an electrolytic plated film at the opposite side and the electroless plated film located at the side of the insulating layer is formed so as to follow to the roughened surface of the insulating layer. This printed wiring board is produced by a semi-additive method wherein the electroless plated film is formed on the roughened surface of the insulating layer so as to follow to the roughened surface of the insulating layer.

Abstract translation: 本发明提出一种制造印刷电路板的技术，该印刷电路板在不引起电镀抗蚀剂剥离的情况下，通过半添加工艺，在化学镀膜和构成导体电路的电解电镀膜之间具有优异的粘合性，并且是印刷 布线板包括形成在绝缘层的粗糙表面上的导体电路，其中导体电路由绝缘层侧面的无电解电镀膜和位于绝缘层侧面的电镀电镀膜和位于 绝缘层的一侧形成为与绝缘层的粗糙化表面相邻。 该印刷电路板是通过半附加法制造的，其中无电镀膜形成在绝缘层的粗糙化表面上，以便遵循绝缘层的粗糙化表面。

公开(公告)号：US06534723B1

公开(公告)日：2003-03-18

申请号：US09821460

申请日：2001-04-06

Applicant: Motoo Asai ,  Takashi Kariya

Inventor： Motoo Asai ,  Takashi Kariya

IPC: H05K103

CPC classification number: H05K3/4617 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/09563 ,  H05K2201/096

Abstract: A multilayer printed-circuit board is provided which is formed by stacking one on the other a plurality of circuit boards, each including a hard insulative substrate having a conductor circuit formed on one or either side thereof, and having formed therein via-holes formed through the hard insulative substrate to extend to the conductor circuit and each filled with a conductive substance, with an adhesive applied between the plurality of circuit boards, and heating and pressing the circuit boards together. One of the outermost ones of the stacked circuit boards has formed on the surface thereof conductive bumps each positioned right above the via-hole and electrically connected to the via-hole, and the other outermost one of the stacked circuit boards has formed on the surface thereof conductive pin or balls each positioned right above the via-hole and electrically connected to the via-hole. This multilayer printed-circuit board is used as a package circuit board and electronic components such as LSI chip are mounted on it to form a semiconductor device. The multilayer printed-circuit board is used as a core substrate, and a build-up wiring layer is formed on one or either side of the core multilayer circuit board. Solder bumps are formed on the surface of one outermost conductor circuit of the build-up wiring layer and conductive pins or balls are provided on the surface of the other outermost conductor circuit of the build-up wiring layer. Thus, a multilayer printed-circuit board is provided on which wiring can be made densely and also electronic components can be mounted with a high density.

Abstract translation: 提供了一种多层印刷电路板，其通过将多个电路板彼此堆叠而形成，每个电路板包括形成在其一侧或两侧上的具有导体电路的硬绝缘基板，并且其中形成有通孔 所述硬绝缘基板延伸到所述导体电路并且各自填充有导电物质，并且将粘合剂施加在所述多个电路板之间，并且将所述电路板加热和加压在一起。 堆叠电路板中最外层的电路板之一在表面上形成有位于通孔正上方的导电凸块，并且电连接到通孔，而另一个最外面的堆叠电路板形成在表面上 其导电针或球各自位于通孔的正上方并电连接到通孔。 该多层印刷电路板用作封装电路板，并且其上安装诸如LSI芯片的电子部件以形成半导体器件。 将多层印刷电路板用作芯基板，并且在芯多层电路板的一侧或任一侧上形成积层布线层。 在叠层布线层的一个最外侧的导体电路的表面上形成有焊料凸点，并且在叠层布线层的另一个最外侧的导体电路的表面设置有导电针或球。 因此，提供一种多层印刷电路板，其上可以致密地制造布线，并且还可以以高密度安装电子部件。

公开(公告)号：US08507806B2

公开(公告)日：2013-08-13

申请号：US12488224

申请日：2009-06-19

Applicant: Takashi Kariya ,  Toshiki Furutani ,  Takeshi Kawanishi

Inventor： Takashi Kariya ,  Toshiki Furutani ,  Takeshi Kawanishi

IPC: H05K1/16

CPC classification number: H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2224/05599

Abstract: A circuit wiring board including a wiring substrate, and a heat resistant substrate accommodated in the wiring substrate and including a core substrate and a through hole conductor formed in the core substrate, the core substrate having a first surface and a second surface on an opposite side of the first surface, the through hole conductor providing electrical connection through the core substrate between the first surface and the second surface of the core substrate.

Abstract translation: 一种电路布线板，包括布线基板和容纳在所述布线基板中的耐热基板，所述布线基板包括形成在所述芯基板中的芯基板和通孔导体，所述芯基板具有第一表面和位于相对侧的第二表面 所述通孔导体在所述芯基板的所述第一表面和所述第二表面之间提供通过所述芯基板的电连接。

公开(公告)号：US20120212919A1

公开(公告)日：2012-08-23

申请号：US13360201

申请日：2012-01-27

Applicant: Yasuhiko MANO ,  Shinobu Kato ,  Takashi Kariya

Inventor： Yasuhiko MANO ,  Shinobu Kato ,  Takashi Kariya

IPC: H05K7/06 ,  H05K1/02 ,  H05K3/30 ,  H05K1/16

CPC classification number: H05K3/4602 ,  H01F17/0033 ,  H01F2017/004 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/0032 ,  H05K2201/1003 ,  H05K2203/1469 ,  H05K2203/1572 ,  Y10T29/4913

Abstract: A printed wiring board includes a core substrate having a cavity and having first and second surfaces, an inductor component accommodated in the cavity, a filler resin filling a gap formed between the substrate and component in the cavity, and a buildup layer formed on the first surface of the substrate and the component. The component has a coil layer, a second insulation layer formed on the coil layer, an electrode formed on the substance layer, and a via conductor formed in the substance layer and connecting the coil layer and the electrode, the component is accommodated in the cavity such that the electrode faces the first surface of the substrate, and the buildup layer includes an interlayer insulation layer formed on the first surface of the substrate and the component, a conductive layer formed on the insulation layer, and a connection via conductor connecting the conductive layer and electrode.

Abstract translation: 一种印刷电路板包括具有空腔并具有第一和第二表面的芯基板，容纳在空腔中的电感器部件，填充在基板和空腔中的部件之间形成的间隙的填充树脂，以及形成在第一 基板表面和部件。 该部件具有线圈层，形成在线圈层上的第二绝缘层，形成在物质层上的电极和形成在物质层中并连接线圈层和电极的通孔导体，该部件容纳在腔体 使得电极面对衬底的第一表面，并且积聚层包括形成在衬底的第一表面上的层间绝缘层和构件，形成在绝缘层上的导电层，以及连接导体 层和电极。

公开(公告)号：US08169792B2

公开(公告)日：2012-05-01

申请号：US12984644

申请日：2011-01-05

Applicant: Takashi Kariya ,  Toshiki Furutani

Inventor： Takashi Kariya ,  Toshiki Furutani

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0271 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49151 ,  Y10T29/49162 ,  H01L2224/0401

Abstract: A multilayer printed wiring board includes: a build-up layer that is formed on a core substrate and has a conductor pattern disposed on an upper surface; a low elastic modulus layer that is formed on the build-up layer; lands that are disposed on an upper surface of the low elastic modulus layer and connected via solder bumps to a IC chip; and conductor posts that pass through the low elastic modulus layer and electrically connect lands with conductor patterns. The conductor posts have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 μm, and the aspect ratio Rasp of external conductor posts, which are positioned at external portions of the low elastic modulus layer, is greater than or equal to the aspect ratio Rasp of internal conductor posts, which are positioned at internal portions of the low elastic modulus layer.

Abstract translation: 多层印刷布线板包括：形成在芯基板上并具有布置在上表面上的导体图案的堆积层; 形成在积层层上的低弹性模量层; 在低弹性模量层的上表面配置并通过焊锡凸块与IC芯片连接的焊盘; 以及穿过低弹性模量层并将焊盘电连接到导体图案的导体柱。 导体柱的长径比Rasp（高度/最小直径）不小于4，最小直径超过30μm，外部导体柱的纵横比Rasp位于低弹性模量层的外部， 大于或等于位于低弹性模量层的内部的内部导体柱的纵横比Rasp。

公开(公告)号：US08091223B2

公开(公告)日：2012-01-10

申请号：US12163252

申请日：2008-06-27

Applicant: Takashi Kariya ,  Toshiki Furutani

Inventor： Takashi Kariya ,  Toshiki Furutani

IPC: H05K3/10

Abstract: A method for manufacturing a board with a built-in electronic element, includes providing a support substrate including a support base and a metal foil, forming a protective film made of a metal material on the metal foil of the support substrate, forming a conductive pattern made of a metal material on the protective film by an additive method, placing an electronic element on the support substrate with the conductive pattern such that a surface of the electronic element where a circuit is formed faces the conductive pattern, covering the electronic element with an insulative resin, etching away the metal foil using a first etching solution such that the protective film is not dissolved by the first etching solution or that the protective film has an etching speed which is slower than an etching speed of the metal foil, and electrically connecting terminals of the electronic element and a part of the conductive pattern.

公开(公告)号：US08079142B2

公开(公告)日：2011-12-20

申请号：US12273939

申请日：2008-11-19

Applicant: Hajime Sakamoto ,  Tadashi Sugiyama ,  Dongdong Wang ,  Takashi Kariya

Inventor： Hajime Sakamoto ,  Tadashi Sugiyama ,  Dongdong Wang ,  Takashi Kariya

IPC: H01K3/10 ,  H05K1/16 ,  H05K7/10

CPC classification number: H01L24/29 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L24/83 ,  H01L25/03 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/18162 ,  H01L2924/30107 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09918 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A method for manufacturing a printed circuit board, including providing a core substrate and an electronic component contained in the core substrate, the electronic component having a die pad, forming a positioning mark on the core substrate, forming an interlayer insulating layer over the core substrate and the electronic component, forming a via hole opening connecting to the die pad of the electronic component through the interlayer insulating layer in accordance with the positioning mark on the core substrate, and forming a via hole structure in the via hole opening in the interlayer insulating layer such that the via hole structure is electrically connected to the die pad.

Abstract translation: 一种制造印刷电路板的方法，包括提供芯基板和包含在芯基板中的电子部件，具有芯片焊盘的电子部件，在芯基板上形成定位标记，在芯基板上形成层间绝缘层 和所述电子部件，根据所述芯基板上的定位标记，通过所述层间绝缘层形成连接到所述电子部件的所述管芯焊盘的通孔开口，以及在所述层间绝缘体的通孔开口部形成通孔结构 使得通孔结构电连接到管芯焊盘。

公开(公告)号：US20110240357A1

公开(公告)日：2011-10-06

申请号：US13050217

申请日：2011-03-17

Applicant: Takashi Kariya ,  Toshiki Furutani

Inventor： Takashi Kariya ,  Toshiki Furutani

IPC: H05K1/11 ,  H05K3/36 ,  H05K3/42

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2924/15151 ,  H01L2924/15311 ,  H05K1/181 ,  H05K1/182 ,  H05K3/0047 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/10159 ,  H05K2201/10363 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A wiring board including a first substrate having a penetrating hole penetrating through the first substrate, a built-up layer formed on one surface of the first substrate and including multiple interlayer resin insulation layers and wiring layers, the built-up layer having an opening portion communicated with the penetrating hole of the first substrate and opened to the outermost surface of the built-up layer, an interposer accommodated in the opening portion of the built-up layer and including a second substrate and a wiring layer formed on the second substrate, the wiring layer of the interposer including multiple conductive circuits for being connected to multiple semiconductor elements, and a filler filling the opening portion of the built-up layer such that the interposer is held in the opening portion of the built-up layer. The opening portion of the built-up layer has a tapered portion tapering toward the outermost surface of the built-up layer.

Abstract translation: 一种布线基板，包括具有穿透所述第一基板的穿透孔的第一基板，形成在所述第一基板的一个表面上并且包括多个层间树脂绝缘层和布线层的积层，所述积层具有开口部 与第一基板的贯通孔相通并且向组合层的最外表面开口，插入物容纳在积层的开口部分中，并且包括形成在第二基板上的第二基板和布线层， 插入器的布线层包括用于连接到多个半导体元件的多个导电电路，以及填充积层的开口部分的填充物，使得插入器被保持在积层的开口部分中。 积层的开口部分具有朝向堆积层的最外表面渐缩的锥形部分。