摘要:
By patterning an underbump metallization layer stack (105) on the basis of a dry etch process (111), significant advantages may be achieved compared to conventional techniques involving a highly complex wet chemical etch process. In particular embodiments, a titanium tungsten layer or any other appropriate last layer (105B) of an underbump metallization layer stack (105) may be etched on the basis of a plasma etch process (107) using a fluorine-based chemistry and oxygen as a physical component. Moreover, appropriate cleaning processes (110, 113) may be performed for removing particles (109) and residues (112) prior to and after the plasma-based patterning process (107).
摘要:
Embodiments of the invention include a microelectronic device that includes a layer dielectric material that includes a feature with a depression. A Nickel barrier layer is formed in the depression of the feature and a first conductive layer is formed in the depression of the feature. The microelectronic device can optionally include a second conductive layer formed below the depression of the feature.
摘要:
Die vorliegende Erfindung betrifft ein Verfahren zum Bonden einer ersten zumindest teilweise metallischen Kontaktfläche eines ersten Substrats (1, 1') mit einer zweiten zumindest teilweise metallischen Kontaktfläche eines zweiten Substrats mit folgenden Schritten, insbesondere folgendem Ablauf: - Aufbringen einer in dem Material mindestens einer der Kontaktflächen zumindest teilweise, insbesondere überwiegend, lösbaren Opferschicht (4) auf mindestens eine der Kontaktflächen, - Bonden der Kontaktflächen unter zumindest teilweisem Lösen der Opferschicht (4) in mindestens einer der Kontaktflächen. Die Kontaktflächen können vollflächig an einem Bondbereich (3) angeordnet sein. Alternativ können die Kontaktflächen aus mehreren Bondbereichen (3') ausgebildet sein, die von Bulkmaterial (5) umgeben oder in Substratkavitäten (2) angeordnet sind. Zur Erzeugung eines Pre-Bonds zwischen den Substraten kann eine Flüssigkeit (z.B. Wasser) verwendet werden.
摘要:
Embodiments of the present invention generally relate to a method for cleaning a processing chamber during substrate processing. During a first substrate processing step, a plasma is formed from a gas mixture of argon, helium, and hydrogen in the processing chamber. In a second substrate processing step, an argon plasma is formed in the processing chamber.
摘要:
A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to "bleed" laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.
摘要:
Semiconductor chip (2) having a first main side (10) and an integrated circuit structure (3) integrated on a semiconductor substrate (9) at the first main side (10). The semiconductor chip (2) further has a contact pad (4A) and an under-bump metallization layer portion (6) being electrically connected to the contact pad (4A). The contact pad (4A) is formed by a part of the integrated circuit structure. The semiconductor chip (2) further has a lead-free solder bump (12) on the under-bump metallization layer portion (6) at the first main side (10) and has an inter-metallic compound layer formed on the under-bump metallization layer portion (6) out of the lead-free solder bump (12). The inter-metallic compound layer contains crystals that have an aspect ratio larger than two, preferably larger than five, and more preferably larger than ten.
摘要:
By patterning an underbump metallization layer stack (105) on the basis of a dry etch process (111), significant advantages may be achieved compared to conventional techniques involving a highly complex wet chemical etch process. In particular embodiments, a titanium tungsten layer or any other appropriate last layer (105B) of an underbump metallization layer stack (105) may be etched on the basis of a plasma etch process (107) using a fluorine-based chemistry and oxygen as a physical component. Moreover, appropriate cleaning processes (110, 113) may be performed for removing particles (109) and residues (112) prior to and after the plasma-based patterning process (107).
摘要:
Procédé de collage direct d'une puce électronique (100) sur un substrat (102) ou sur une autre puce électronique, comportant les étapes de : - traitement hydrophile d'une partie (105) d'une face de la puce électronique et d'une partie (110) d'une face (108) du substrat ou de l'autre puce électronique; - dépôt d'un fluide aqueux (112) sur la partie de la face du substrat ou de la deuxième puce électronique; - dépôt de la partie de la face de la puce électronique sur le fluide aqueux; - séchage du fluide aqueux jusqu'à une solidarisation de la partie de la face de la puce électronique avec la partie de la face du substrat ou de l'autre puce électronique; et comportant en outre, pendant au moins une partie du séchage du fluide aqueux, une émission d'ultrasons dans le fluide aqueux à travers le substrat ou l'autre puce électronique.