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公开(公告)号:WO2015159579A1
公开(公告)日:2015-10-22
申请号:PCT/JP2015/054123
申请日:2015-02-16
Applicant: 三菱電機株式会社
IPC: H01L21/28 , H01L21/3205 , H01L21/329 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/41 , H01L29/47 , H01L29/872
CPC classification number: H01L24/13 , H01L23/3135 , H01L23/3192 , H01L23/36 , H01L23/3735 , H01L23/564 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/33 , H01L29/1608 , H01L29/401 , H01L29/47 , H01L29/6606 , H01L29/872 , H01L2224/02166 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0347 , H01L2224/03614 , H01L2224/03914 , H01L2224/04026 , H01L2224/05084 , H01L2224/05085 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05187 , H01L2224/05556 , H01L2224/05562 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/06181 , H01L2224/10126 , H01L2224/13082 , H01L2224/13147 , H01L2224/13582 , H01L2224/13611 , H01L2224/13624 , H01L2224/13639 , H01L2224/13644 , H01L2224/13655 , H01L2224/33181 , H01L2924/00014 , H01L2924/05042 , H01L2924/10272 , H01L2924/12032 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/04941 , H01L2224/056 , H01L2224/051 , H01L2924/00 , H01L2924/00012
Abstract: 本発明は、高温動作においてもCu配線の酸化を抑制する半導体装置の提供を目的とする。本発明に係る半導体装置は、主面を有する基板1と、基板1の主面の側に選択的に形成されたCu電極8と、Cu電極8の上面にその端部を除いて形成された酸化防止膜14と、基板1の主面上に形成され、Cu電極8の側面および上面の端部を覆う有機樹脂膜10と、有機樹脂膜10と基板1の主面との間、並びに有機樹脂膜10とCu電極8の側面および上面の端部との間に、両者に接して形成される拡散防止膜11と、を備える。
Abstract translation: 本发明的目的在于提供即使在高温运转时也抑制Cu布线的氧化的半导体装置。 根据本发明的半导体器件具有:具有主表面的衬底(1); 选择性地形成在基板(1)的主表面侧上的Cu电极(8); 除了上表面的边缘部分之外,形成在Cu电极(8)的上表面上的防氧化膜(14) 形成在基板(1)的主面上并覆盖Cu电极(8)的上表面的侧面和边缘部分的有机树脂膜(10); 和形成在所述有机树脂膜(10)和所述基板(1)的主面之间且所述有机树脂膜(10)与所述侧面和所述上表面的边缘部分之间的扩散防止膜(11) 的铜电极(8)的上表面的侧面和边缘部分与所述有机树脂膜(10)接触。
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公开(公告)号:WO2015003163A1
公开(公告)日:2015-01-08
申请号:PCT/US2014045468
申请日:2014-07-03
Applicant: TEXAS INSTRUMENTS INC , TEXAS INSTRUMENTS JAPAN
Inventor: WANG JING , LIN LIN , JIA QIULING , YANG QI , LIU JIANXIN
CPC classification number: H01L24/05 , H01L23/3192 , H01L23/49524 , H01L23/49562 , H01L23/522 , H01L24/03 , H01L24/73 , H01L29/7802 , H01L2224/0345 , H01L2224/0346 , H01L2224/03614 , H01L2224/0362 , H01L2224/04042 , H01L2224/05026 , H01L2224/05155 , H01L2224/05564 , H01L2224/05573 , H01L2224/05639 , H01L2224/05644 , H01L2224/32245 , H01L2224/40247 , H01L2224/48247 , H01L2224/73265 , H01L2224/94 , H01L2924/10253 , H01L2924/1033 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2224/03 , H01L2924/00012 , H01L2924/00 , H01L2924/00014 , H01L2224/05139 , H01L2224/05144
Abstract: In described examples, a dielectric stack is formed, including a bottom dielectric layer (211) and a top dielectric layer (212) having a contact hole (239) over a bond pad (215). An outer edge of the bottom dielectric layer (211) within the contact hole (239) extends beyond an outer edge of the top dielectric layer (212) to define an exposed bond pad area having a bond pad edge. A first metal layer (226) is deposited. A second metal layer (227) is deposited on the first metal layer (226). The second metal layer (227) is wet etched to recess it from sidewalls of the bottom dielectric layer (211) in the contact hole (239). The first metal layer (226) is wet etched to recess it from the top dielectric layer (212). The first metal layer (226) extends over the bond pad edge onto the bottom dielectric layer (211).
Abstract translation: 在所述实施例中,形成介电叠层,其包括底部电介质层(211)和在接合焊盘(215)上方具有接触孔(239)的顶部电介质层(212)。 接触孔(239)内的底部电介质层(211)的外边缘延伸超过顶部电介质层(212)的外边缘以限定具有接合焊盘边缘的暴露的接合焊盘区域。 沉积第一金属层(226)。 第二金属层(227)沉积在第一金属层(226)上。 第二金属层(227)被湿式蚀刻以将其从接触孔(239)中的底部电介质层(211)的侧壁凹陷。 湿法蚀刻第一金属层(226)以使其从顶部介电层(212)凹陷。 第一金属层(226)在接合焊盘边缘上延伸到底部电介质层(211)上。
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3.INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY 审中-公开
Title translation: 使用顶尖后置技术和底部结构技术的集成电路芯片公开(公告)号:WO2010114687A1
公开(公告)日:2010-10-07
申请号:PCT/US2010/027056
申请日:2010-03-11
Applicant: MEGICA CORPORATION , LIN, Mou-Shiung , LEE, Jin-Yuan , LO, Hsin-Jung , YANG, Ping-Jung , LIU, Te-Sheng
Inventor: LIN, Mou-Shiung , LEE, Jin-Yuan , LO, Hsin-Jung , YANG, Ping-Jung , LIU, Te-Sheng
CPC classification number: G06F1/16 , G11C5/147 , H01L21/563 , H01L23/3128 , H01L23/3171 , H01L23/3192 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L23/60 , H01L23/66 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/50 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2223/6611 , H01L2223/6666 , H01L2224/02166 , H01L2224/02311 , H01L2224/02313 , H01L2224/02321 , H01L2224/0233 , H01L2224/02331 , H01L2224/0235 , H01L2224/0237 , H01L2224/02371 , H01L2224/02375 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/03612 , H01L2224/03614 , H01L2224/03912 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05024 , H01L2224/05027 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05176 , H01L2224/05181 , H01L2224/05187 , H01L2224/05541 , H01L2224/05548 , H01L2224/05554 , H01L2224/0556 , H01L2224/05567 , H01L2224/05572 , H01L2224/056 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/05673 , H01L2224/05676 , H01L2224/11 , H01L2224/11009 , H01L2224/1132 , H01L2224/11334 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/119 , H01L2224/1191 , H01L2224/13 , H01L2224/13006 , H01L2224/1302 , H01L2224/13022 , H01L2224/13024 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13099 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2224/13294 , H01L2224/133 , H01L2224/13311 , H01L2224/13609 , H01L2224/1403 , H01L2224/1411 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/16265 , H01L2224/17181 , H01L2224/2919 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/29339 , H01L2224/32105 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48111 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48664 , H01L2224/48669 , H01L2224/48764 , H01L2224/48769 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/48864 , H01L2224/4911 , H01L2224/49175 , H01L2224/4918 , H01L2224/73203 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2224/81191 , H01L2224/81411 , H01L2224/81444 , H01L2224/81801 , H01L2224/81815 , H01L2224/8185 , H01L2224/81895 , H01L2224/81903 , H01L2224/83101 , H01L2224/83104 , H01L2224/83851 , H01L2224/92 , H01L2224/9202 , H01L2224/92125 , H01L2224/92127 , H01L2224/92147 , H01L2224/92225 , H01L2224/92247 , H01L2224/94 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/06589 , H01L2225/1023 , H01L2225/1029 , H01L2225/1058 , H01L2225/107 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01056 , H01L2924/01059 , H01L2924/01068 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/12041 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1421 , H01L2924/1433 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/19105 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48869 , H01L2224/48744 , H01L2924/00012 , H01L2224/03 , H01L2224/0361 , H01L2924/0665 , H01L2224/81 , H01L2224/83 , H01L24/78 , H01L2224/85 , H01L21/56 , H01L21/78 , H01L2924/0635 , H01L2924/07025 , H01L21/304 , H01L21/76898 , H01L2224/0231
Abstract: Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
Abstract translation: 公开了集成电路芯片和芯片封装,其包括在集成电路芯片的顶部处的过钝化方案,以及使用顶部后钝化技术和底部结构技术的集成电路芯片的底部的底部方案。 集成电路芯片可以通过过钝化方案或者通过钝化方案连接到外部电路或结构,例如球栅阵列(BGA)衬底,印刷电路板,半导体芯片,金属衬底,玻璃衬底或陶瓷衬底 底部方案。 描述了相关的制造技术。
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公开(公告)号:WO2015198839A1
公开(公告)日:2015-12-30
申请号:PCT/JP2015/066351
申请日:2015-06-05
Applicant: ソニー株式会社
CPC classification number: H01L24/16 , H01L21/563 , H01L21/6836 , H01L23/12 , H01L23/3121 , H01L23/3142 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/03 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2221/68327 , H01L2221/6834 , H01L2224/0345 , H01L2224/03614 , H01L2224/0381 , H01L2224/03912 , H01L2224/05166 , H01L2224/05173 , H01L2224/05647 , H01L2224/10175 , H01L2224/1146 , H01L2224/11462 , H01L2224/1147 , H01L2224/1181 , H01L2224/11849 , H01L2224/119 , H01L2224/13014 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/14133 , H01L2224/14136 , H01L2224/16013 , H01L2224/16055 , H01L2224/16057 , H01L2224/16058 , H01L2224/16227 , H01L2224/16237 , H01L2224/16503 , H01L2224/2919 , H01L2224/2929 , H01L2224/29387 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73204 , H01L2224/81011 , H01L2224/81012 , H01L2224/81065 , H01L2224/81075 , H01L2224/8112 , H01L2224/81121 , H01L2224/81143 , H01L2224/81191 , H01L2224/81201 , H01L2224/81203 , H01L2224/81204 , H01L2224/8121 , H01L2224/81385 , H01L2224/81444 , H01L2224/81815 , H01L2224/81893 , H01L2224/81906 , H01L2224/81907 , H01L2224/8191 , H01L2224/81935 , H01L2224/81986 , H01L2224/831 , H01L2224/83104 , H01L2224/83192 , H01L2224/83204 , H01L2224/83862 , H01L2224/83907 , H01L2224/92 , H01L2224/9211 , H01L2224/92125 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06562 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/00015 , H01L2924/01028 , H01L2924/01046 , H01L2924/01079 , H01L2924/014 , H01L2924/15151 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2924/351 , H01L2924/381 , H01L2924/3841 , H05K1/111 , H05K3/3436 , H05K3/3452 , H05K2201/09227 , H05K2201/09663 , H05K2201/0979 , H05K2201/0989 , H05K2201/10674 , Y02P70/611 , Y02P70/613 , H01L2924/00012 , H01L2224/16225 , H01L2924/00 , H01L2224/81 , H01L2224/83 , H01L2924/05442 , H01L2924/01047 , H01L2924/01074 , H01L2224/814 , H01L2224/45099 , H01L2221/68304 , H01L21/304 , H01L2221/68381 , H01L21/78 , H01L2224/03 , H01L2224/11
Abstract: 半導体チップは、チップ本体と、チップ本体の素子形成面に設けられたはんだを含む複数の電極とを有する。パッケージ基板は、基板本体と、基板本体の表面に設けられた複数の配線およびソルダレジスト層とを有する。はんだを含む複数の電極は、第1の電位を供給する複数の第1電極と、第1の電位とは異なる第2の電位を供給する複数の第2電極とを含む。複数の第1電極および複数の第2電極は、チップ本体の中央部に、行方向および列方向の両方に交互に配置されている。複数の配線は、複数の第1電極を相互に接続する複数の第1配線と、複数の第2電極を相互に接続する複数の第2配線とを含む。
Abstract translation: 本发明的半导体芯片包括主芯片体和设置在所述主芯片体的元件形成表面上的多个焊料包含电极。 封装基板包括:主基板主体; 以及设置在所述主基板主体的表面上的多根导线和阻焊层。 多个含焊料的电极包括提供第一电位的多个第一电极和提供不同于第一电位的第二电位的多个第二电极。 多个第一电极和多个第二电极在主芯片体的中间沿行方向和列方向交替布置。 上述多根线包括将多个第一电极彼此连接的多条第一线和将多个第二电极彼此连接的多条第二线。
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公开(公告)号:WO2014033977A1
公开(公告)日:2014-03-06
申请号:PCT/JP2013/001915
申请日:2013-03-21
Applicant: パナソニック株式会社
Inventor: 樋口 裕一
IPC: H01L21/60 , H01L25/065 , H01L25/07 , H01L25/18
CPC classification number: H01L25/0657 , H01L21/563 , H01L23/481 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/02372 , H01L2224/0239 , H01L2224/0345 , H01L2224/03462 , H01L2224/03614 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05011 , H01L2224/05012 , H01L2224/05015 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05166 , H01L2224/05187 , H01L2224/05551 , H01L2224/05552 , H01L2224/05555 , H01L2224/05557 , H01L2224/05558 , H01L2224/05559 , H01L2224/05573 , H01L2224/05582 , H01L2224/05609 , H01L2224/05611 , H01L2224/05613 , H01L2224/05617 , H01L2224/05618 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05666 , H01L2224/05684 , H01L2224/1145 , H01L2224/11462 , H01L2224/13014 , H01L2224/13017 , H01L2224/13019 , H01L2224/13024 , H01L2224/13025 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13117 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13166 , H01L2224/13184 , H01L2224/16014 , H01L2224/16058 , H01L2224/16148 , H01L2224/16237 , H01L2224/32145 , H01L2224/73104 , H01L2224/73204 , H01L2224/8112 , H01L2224/81121 , H01L2224/8114 , H01L2224/81141 , H01L2224/81143 , H01L2224/81193 , H01L2224/81201 , H01L2224/83862 , H01L2224/92125 , H01L2225/06513 , H01L2225/06541 , H01L2225/06548 , H01L2225/06593 , H01L2924/01032 , H01L2924/207 , H01L2924/2075 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/381 , H01L2924/384 , H01L2224/16225 , H01L2224/32225 , H01L2924/00012 , H01L2924/00014 , H01L2924/04953 , H01L2924/014 , H01L2924/01022 , H01L2924/01029
Abstract: 第1の半導体チップ(100)と第2の半導体チップ(200)とが接合された積層チップを有する半導体装置である。第1の半導体チップの主面上には、第1の電極パッド(110)と、第1の電極パッドの上に形成された第1のバンプ(120)とが形成されている。第2の半導体チップ(200)の主面上には、第1のバンプと接合するように第2のバンプ(220)が形成されている。第1の電極パッド(110)は、中央に段差状となる開口部を有している。第1のバンプ(120)は、第1の電極パッド(110)における開口部とその周辺部との段差状に跨るように形成された中央が窪んだ凹状を有する。
Abstract translation: 该半导体器件具有通过接合第一半导体芯片(100)和第二半导体芯片(200)而产生的层叠芯片。 在第一半导体芯片的主表面上形成有形成在第一电极焊盘上的第一电极焊盘(110)和第一凸块(120)。 在第二半导体芯片(200)的主表面上形成有用于与第一凸块接合的第二凸块(220)。 第一电极焊盘(110)具有孔,使得中心部分具有阶梯形状。 第一凸块(120)具有中心部分凹陷的凹陷形状,以便跨越第一电极焊盘(110)的孔径和周边部分的阶梯形状。
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公开(公告)号:WO2013076587A2
公开(公告)日:2013-05-30
申请号:PCT/IB2012003029
申请日:2012-09-28
Applicant: ADVANCED TECH MATERIALS
Inventor: KOJIMA TSUTOMU , KOJI YUKICHI
CPC classification number: C23F1/18 , C23F1/34 , C23F1/44 , H01L21/32134 , H01L21/76865 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/03614 , H01L2224/03826 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/1146 , H01L2224/1147 , H01L2224/13009 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/12044 , H01L2924/1461 , H01L2924/01079 , H01L2924/00 , H01L2224/05552
Abstract: [Problem] The purpose of the present invention is to provide an etching agent for a process for etching copper or a copper alloy from an electronic substrate that includes both nickel, and copper or a copper alloy, wherein said etching agent foams little during use and can highly selectively etch copper or a copper alloy. [Solution] An etching agent used in a process for selectively etching copper or a copper alloy from an electronic substrate that includes both nickel, and copper or a copper alloy, said etching agent for copper or a copper alloy having as essential components: a chain-like alkanolamine (A); a chelating agent (B) having an acid group within molecules thereof; and hydrogen peroxide (C).
Abstract translation: 本发明的目的是提供一种用于从包括镍和铜或铜合金的电子基板蚀刻铜或铜合金的方法的蚀刻剂,其中所述蚀刻剂在使用期间泡沫很少, 可以高选择性地蚀刻铜或铜合金。 [解决方案]用于从包括镍和铜或铜合金的电子基板选择性地蚀刻铜或铜合金的工艺中使用的蚀刻剂,所述用于铜的蚀刻剂或作为必要成分的铜合金:链条 样链烷醇胺(A); 在其分子内具有酸基的螯合剂(B); 和过氧化氢(C)。
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公开(公告)号:WO2012024300A2
公开(公告)日:2012-02-23
申请号:PCT/US2011047927
申请日:2011-08-16
Applicant: ADVANCED TECH MATERIALS , YOSHIDA YUTAKA , KOJI YUKICHI
Inventor: YOSHIDA YUTAKA , KOJI YUKICHI
CPC classification number: C23F1/18 , C23F1/44 , H01L21/32134 , H01L21/76885 , H01L21/76898 , H01L24/03 , H01L2224/0346 , H01L2224/03614 , H01L2224/0401 , H01L2224/05647 , H01L2224/11 , H01L2224/11912 , H01L2224/13083 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/00 , H01L2924/00012
Abstract: A solution for selectively etching copper or a copper alloy from a microelectronic device, wherein the device simultaneously includes copper or a copper alloy and nickel-containing material, the solution being an etching solution for copper or a copper alloy comprising a chelating agent having an acid group in a molecule, hydrogen peroxide, and a surfactant having an oxyethylene chain in a molecule.
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8.METHODS AND DEVICES FOR FABRICATING AND ASSEMBLING PRINTABLE SEMICONDUCTOR ELEMENTS 审中-公开
Title translation: 用于制作和组装可印刷的半导体元件的方法和装置公开(公告)号:WO2005122285A2
公开(公告)日:2005-12-22
申请号:PCT/US2005/019354
申请日:2005-06-02
Applicant: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS , NUZZO, Ralph, G. , ROGERS, John, A. , MENARD, Etienne , LEE, Keon Jae , KHANG, Dahl-Young , SUN, Yugang , MEITL, Matthew , ZHU, Zhengtao
Inventor: NUZZO, Ralph, G. , ROGERS, John, A. , MENARD, Etienne , LEE, Keon Jae , KHANG, Dahl-Young , SUN, Yugang , MEITL, Matthew , ZHU, Zhengtao
IPC: H01L31/0312
CPC classification number: H01L29/76 , B81C2201/0185 , B82Y10/00 , H01L21/02521 , H01L21/02603 , H01L21/02628 , H01L21/308 , H01L21/322 , H01L21/6835 , H01L23/02 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/83 , H01L24/94 , H01L24/97 , H01L25/0753 , H01L27/1285 , H01L27/1292 , H01L29/04 , H01L29/06 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/12 , H01L29/78603 , H01L29/78681 , H01L29/78696 , H01L31/0392 , H01L31/03926 , H01L31/1804 , H01L31/1864 , H01L31/1896 , H01L33/007 , H01L33/0079 , H01L33/32 , H01L2221/68368 , H01L2221/68381 , H01L2224/03 , H01L2224/0332 , H01L2224/0345 , H01L2224/03614 , H01L2224/0362 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05644 , H01L2224/05666 , H01L2224/08225 , H01L2224/2919 , H01L2224/32225 , H01L2224/80 , H01L2224/80006 , H01L2224/80121 , H01L2224/80862 , H01L2224/80895 , H01L2224/83 , H01L2224/83005 , H01L2224/83121 , H01L2224/83192 , H01L2224/83193 , H01L2224/8385 , H01L2224/83862 , H01L2224/9202 , H01L2224/94 , H01L2224/95 , H01L2224/97 , H01L2924/00012 , H01L2924/01032 , H01L2924/0665 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12036 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043 , H01L2924/12044 , H01L2924/1305 , H01L2924/1306 , H01L2924/13063 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15159 , H01L2924/15162 , H01L2924/15788 , H01L2924/1579 , Y02E10/547 , Y02P70/521 , Y10S977/707 , Y10S977/724 , H01L2924/00014 , H01L2924/00
Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.
Abstract translation: 本发明提供了用于制造可印刷半导体元件并将可印刷半导体元件组装到衬底表面上的方法和装置。 本发明的方法,装置和装置部件能够在包含聚合物材料的基底上产生宽范围的灵活的电子和光电器件和器件阵列。 本发明还提供了拉伸配置中能够具有良好性能的可拉伸半导体结构和可拉伸电子器件。
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公开(公告)号:WO2016075791A1
公开(公告)日:2016-05-19
申请号:PCT/JP2014/080072
申请日:2014-11-13
Applicant: ルネサスエレクトロニクス株式会社
IPC: H01L21/3205 , H01L21/768 , H01L23/522
CPC classification number: H01L24/02 , H01L21/3205 , H01L21/768 , H01L23/522 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/02166 , H01L2224/02181 , H01L2224/02185 , H01L2224/0219 , H01L2224/02331 , H01L2224/0235 , H01L2224/02373 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/0346 , H01L2224/03462 , H01L2224/03466 , H01L2224/0347 , H01L2224/035 , H01L2224/03614 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/05007 , H01L2224/05008 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2224/05166 , H01L2224/05176 , H01L2224/0518 , H01L2224/05181 , H01L2224/05184 , H01L2224/05548 , H01L2224/05566 , H01L2224/05567 , H01L2224/05664 , H01L2224/2919 , H01L2224/32225 , H01L2224/4502 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45664 , H01L2224/48095 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/48465 , H01L2224/48664 , H01L2224/48864 , H01L2224/73265 , H01L2924/00014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01046 , H01L2924/04941 , H01L2924/07025 , H01L2924/10253 , H01L2924/1306 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/01008
Abstract: 半導体装置は、複数の配線層の最上層に形成されたパッド電極9aと、パッド電極9a上に開口11aを有する下地絶縁膜11と、下地絶縁膜11上に形成された下地金属膜UMと、下地金属膜UM上に形成された再配線RMと、再配線RMの上面および側面を覆うように形成されたキャップ金属膜CMとを有する。そして、再配線RMの外側の領域において、再配線RMの側壁上に形成されたキャップ金属膜CMと下地絶縁膜11との間には、再配線RMとは別材料の下地金属膜UMと、再配線RMとは別材料のキャップ金属膜CMと、が形成されており、再配線RMの外側の領域において、下地金属膜UMとキャップ金属膜CMとが直接接している。
Abstract translation: 半导体器件具有:形成在多个布线层的最上层上的焊盘电极9a; 基片绝缘膜11,其在焊盘电极9a上具有开口11a; 形成在基底绝缘膜11上的贱金属膜UM; 形成在基底金属膜UM上的再布线RM; 并且形成为覆盖重新布线RM的顶表面和侧表面的帽金属膜CM。 在再配线RM的外侧的区域中,与重新布线RM不同的材料的贱金属薄膜UM和与重新布线RM不同的材料的金属薄膜CM形成在 形成在再配线RM的侧壁上的盖金属膜CM和基底绝缘膜11,以及在重新布线RM,基底金属膜UM和盖金属膜CM的外侧的区域中直接接触。
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10.
公开(公告)号:WO2014207590A2
公开(公告)日:2014-12-31
申请号:PCT/IB2014/061968
申请日:2014-06-05
Applicant: KONINKLIJKE PHILIPS N.V.
Inventor: LEI, Jipu , SCHIAFFINO, Stefano , NICKEL, Alexander H. , NG, Mooi Guan , AKRAM, Salman
IPC: H01L21/60
CPC classification number: H01L24/11 , B23K1/20 , H01L21/4853 , H01L23/49816 , H01L24/03 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L24/94 , H01L2224/0345 , H01L2224/03614 , H01L2224/03912 , H01L2224/0401 , H01L2224/05647 , H01L2224/0603 , H01L2224/06102 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/1182 , H01L2224/11825 , H01L2224/11826 , H01L2224/1184 , H01L2224/11845 , H01L2224/119 , H01L2224/11902 , H01L2224/13017 , H01L2224/13022 , H01L2224/13147 , H01L2224/13564 , H01L2224/13582 , H01L2224/136 , H01L2224/13611 , H01L2224/13639 , H01L2224/13644 , H01L2224/13655 , H01L2224/1403 , H01L2224/14051 , H01L2224/14104 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/81205 , H01L2224/81801 , H01L2224/81815 , H01L2224/94 , H01L2924/12041 , H01L2224/11 , H01L2224/03 , H01L2924/00014 , H01L2924/014 , H01L2924/00012 , H01L2224/1146 , H01L2924/00
Abstract: A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.
Abstract translation: 公开了一种技术,用于使芯片上的焊料凸块的顶表面处于同一平面,以确保芯片和基板之间的更可靠的结合。 该芯片设置有可能具有不同高度的焊盘。 在焊盘之间形成电介质层。 在焊盘上电镀较厚的金属层。 金属层被平坦化以使焊料上方的金属层部分的顶表面位于相同的平面内并在电介质层上方。 在平坦化的金属层部分上沉积基本均匀的薄的焊料层,使得焊料凸块的顶表面基本上在同一平面内。 然后将芯片定位在具有对应的金属焊盘的衬底上,并且焊料被回流或超声波结合到衬底焊盘。
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