公开(公告)号：US20130313707A1

公开(公告)日：2013-11-28

申请号：US13826694

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-il Choi ,  Jeong-woo Park ,  Jeonggi Jin ,  Yeun-Sang Park

IPC: H01L23/00

CPC classification number: H01L24/12 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/13183 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/01024 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552

Abstract: Provided are electrical interconnections and methods for fabricating the same. The electrical interconnection may include a substrate including a bonding pad, a solder ball electrically connected to the bonding pad, a solder supporter on the bonding pad, a portion of the solder ball filling the solder supporter, and a metal layer between the bonding pad and the solder supporter, the metal layer having an ionization tendency lower than the bonding pad.

Abstract translation: 提供电互连及其制造方法。 电互连可以包括：衬底，其包括接合焊盘，与接合焊盘电连接的焊球，焊盘上的焊料支撑体，填充焊料支撑体的焊球的一部分，以及在焊盘和焊盘之间的金属层 所述焊料支撑体，所述金属层的电离倾向低于所述接合焊盘。

公开(公告)号：US20170062308A1

公开(公告)日：2017-03-02

申请号：US15151079

申请日：2016-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-ll Choi ,  Hyo-Ju Kim ,  Yeun-Sang Park ,  Atsushi Fujisaki ,  Kwang-Jin Moon ,  Byung-Lyul Park

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0501 ,  H01L2924/05032 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.

Abstract translation: 一种半导体器件包括穿透衬底的通孔结构，所述通孔结构的一部分在所述衬底的表面上暴露，所述保护层图案结构设置在所述衬底的表面上并且包括第一保护层图案和第二保护 所述第一保护层图案围绕所述通孔结构的所述暴露部分的下侧壁并暴露所述通孔结构的所述暴露部分的上侧壁，所述第二保护层图案暴露所述第一保护的顶表面的一部分 所述衬垫结构设置在所述通孔结构和所述保护层图案结构上并且覆盖由所述第二保护层图案暴露的所述第一保护层图案的顶表面。

公开(公告)号：US20140008815A1

公开(公告)日：2014-01-09

申请号：US13911569

申请日：2013-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeun-Sang Park ,  Byung-Lyul Park ,  SungHee Kang ,  Taeseong Kim ,  Kwangjin Moon ,  Sukchul Bang

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Semiconductor devices are disclosed. The semiconductor device may include a semiconductor substrate having a first surface and a second surface opposite to each other and a pad trench formed at a portion of the second surface, a through-electrode penetrating the semiconductor substrate and protruding from a bottom surface of the pad trench. A buried pad may be disposed in the pad trench and may surround the through-electrode.

Abstract translation: 公开了半导体器件。 半导体器件可以包括具有彼此相对的第一表面和第二表面的半导体衬底和形成在第二表面的一部分处的衬垫沟槽，穿透半导体衬底并从衬底的底表面突出的通孔 沟。 掩埋焊盘可以设置在焊盘沟槽中并且可以围绕通孔。

公开(公告)号：US08816499B2

公开(公告)日：2014-08-26

申请号：US13826694

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il Choi ,  Jeong-Woo Park ,  Jeonggi Jin ,  Yeun-Sang Park

IPC: H01L23/488 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/12 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/13183 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/01024 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552

Abstract: Provided are electrical interconnections and methods for fabricating the same. The electrical interconnection may include a substrate including a bonding pad, a solder ball electrically connected to the bonding pad, a solder supporter on the bonding pad, a portion of the solder ball filling the solder supporter, and a metal layer between the bonding pad and the solder supporter, the metal layer having an ionization tendency lower than the bonding pad.

Abstract translation: 提供电互连及其制造方法。 电互连可以包括：衬底，其包括接合焊盘，与接合焊盘电连接的焊球，焊盘上的焊料支撑体，填充焊料支撑体的焊球的一部分，以及焊接垫和 所述焊料支撑体，所述金属层的电离倾向低于所述接合焊盘。

公开(公告)号：US09530706B2

公开(公告)日：2016-12-27

申请号：US14669291

申请日：2015-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Pil-Kyu Kang ,  Byung Lyul Park ,  Taeyeong Kim ,  Yeun-Sang Park ,  Dosun Lee ,  Ho-Jin Lee ,  Jinho Chun ,  Ju-il Choi ,  Yi Koan Hong

IPC: H01L25/065 ,  H01L21/66 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract translation: 提供具有芯片堆叠和互连端子的半导体器件。 芯片堆叠包括彼此堆叠的第一半导体芯片，第二半导体芯片和第三半导体芯片。 互连端子电耦合到芯片堆叠。 第一半导体芯片包括第一正面和第一背面。 第二半导体芯片包括电耦合到第二电路层并穿透第二半导体芯片的第二前表面，第二背面，第二电路层和贯通电极。 第三半导体芯片包括第三前表面，与第三前表面相对的第三背面和与第三前表面相邻的第三电路层。 第一前表面和第二前表面彼此面对。 第三前表面和第二后侧表面彼此面对。

公开(公告)号：US09287251B2

公开(公告)日：2016-03-15

申请号：US14794561

申请日：2015-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Yeun-Sang Park ,  Jin-Ho An ,  Ho-Jin Lee ,  Joo-Hee Jang ,  Deok-Young Jung

IPC: H01L21/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/76831 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate. A plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.

Abstract translation: 在一种方法中，第一开口形成在第一基板上的第一绝缘中间层中。 在第一开口中形成有与第一扩散防止绝缘图案接触并具有平坦化顶表面的第一导电图案结构。 类似地，在第二基板上的第二绝缘中间层中形成接触第二扩散防止绝缘图案的第二导电图案结构。 在其上分别具有第一和第二导电图案结构的第一和第二基板中的至少一个上执行等离子体处理工艺。 第一和第二导电图案结构彼此接触以接合第一和第二基板。

公开(公告)号：US20160020197A1

公开(公告)日：2016-01-21

申请号：US14794561

申请日：2015-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Yeun-Sang Park ,  Jin-Ho An ,  Ho-Jin Lee ,  Joo-Hee Jang ,  Deok-Young Jung

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/76831 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate, plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.

Abstract translation: 在一种方法中，第一开口形成在第一基板上的第一绝缘中间层中。 在第一开口中形成有与第一扩散防止绝缘图案接触并具有平坦化顶表面的第一导电图案结构。 类似地，在第二基板上的第二绝缘中间层中形成接触第二扩散防止绝缘图案的第二导电图案结构，在其上具有第一和第二导电图案结构的第一和第二基板中的至少一个上执行等离子体处理工艺， ， 分别。 第一和第二导电图案结构彼此接触以接合第一和第二基板。

公开(公告)号：US10020273B2

公开(公告)日：2018-07-10

申请号：US15345614

申请日：2016-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il Choi ,  Hyoju Kim ,  Byunglyul Park ,  Yeun-Sang Park ,  Jubin Seo ,  Atsushi Fujisaki

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13076 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13211 ,  H01L2224/13239 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2224/1146 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01029

Abstract: According to aspects provided herein, a semiconductor device may include a bump providing improved reliability and reduced size. In some aspects, a conductive pad may be formed on a substrate, and a conductive support layer, which may be a pillar, may be formed on the conductive pad. An intermetallic compound (IMC) layer may be formed on the conductive support layer, and a solder layer may be formed on the IMC layer. In some aspects, the conductive support layer may be of a smaller width than the IMC layer. In some aspects, the conductive support layer may have side surfaces which are wider at the solder side than at the conductive pad side. In some aspects, other layers may be formed, such as a seed layer between the conductive pad and the conductive support layer, or a barrier layer between the conductive support layer and the IMC layer.

公开(公告)号：US09728490B2

公开(公告)日：2017-08-08

申请号：US15151079

申请日：2016-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Hyo-Ju Kim ,  Yeun-Sang Park ,  Atsushi Fujisaki ,  Kwang-Jin Moon ,  Byung-Lyul Park

IPC: H01L23/485 ,  H01L23/48 ,  H01L23/31 ,  H01L23/532 ,  H01L23/29 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0501 ,  H01L2924/05032 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.

公开(公告)号：US09653623B2

公开(公告)日：2017-05-16

申请号：US14956382

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan Hong ,  Yeun-Sang Park ,  Byung-Lyul Park ,  Joo-Hee Jang

IPC: H01L31/02 ,  H01L31/0232 ,  H01L23/00

CPC classification number: H01L31/02005 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/91 ,  H01L31/02327 ,  H01L2224/04026 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06505 ,  H01L2224/06517 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/27416 ,  H01L2224/27602 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/29014 ,  H01L2224/29022 ,  H01L2224/2929 ,  H01L2224/30051 ,  H01L2224/3013 ,  H01L2224/3014 ,  H01L2224/3015 ,  H01L2224/3016 ,  H01L2224/32147 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80903 ,  H01L2224/83193 ,  H01L2224/8388 ,  H01L2924/00014

Abstract: In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.