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公开(公告)号：US20240274653A1
公开(公告)日：2024-08-15
申请号：US18635748
申请日：2024-04-15
IPC分类号： H01L27/01 , H01L23/00 , H01L23/522
CPC分类号： H01L28/88 , H01L23/5223 , H01L24/05 , H01L27/01 , H01L28/40 , H01L28/87 , H01L24/13 , H01L2224/02181 , H01L2224/05018 , H01L2224/05559
摘要： A semiconductor device includes first and second metal-insulator-metal structures. The first metal-insulator-metal structure includes a first bottom conductor plate, a first portion of a first dielectric layer, a first middle conductor plate, a first portion of a second dielectric layer, and a first top conductor plate stacked up one over another. The second metal-insulator-metal structure includes a second bottom conductor plate, a second portion of the first dielectric layer, a second middle conductor plate, a second portion of the second dielectric layer, and a second top conductor plate stacked up one over another. In a cross-sectional view, the first bottom conductor plate is wider than the first middle conductor plate that is wider than the first top conductor plate, and the second bottom conductor plate is narrower than the second middle conductor plate that is narrower than the first top conductor plate.
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2.发明公开公开(公告)号：US20240250047A1
公开(公告)日：2024-07-25
申请号：US18598167
申请日：2024-03-07
发明人： TENG-YEN HUANG
IPC分类号： H01L23/00 , H01L25/065
CPC分类号： H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L24/02 , H01L2224/02372 , H01L2224/03001 , H01L2224/03011 , H01L2224/03452 , H01L2224/0361 , H01L2224/03622 , H01L2224/05018 , H01L2224/05073 , H01L2224/05082 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05193 , H01L2224/05546 , H01L2224/05559 , H01L2224/05647 , H01L2224/05657 , H01L2224/05676 , H01L2224/0568 , H01L2224/05684 , H01L2224/0603 , H01L2224/06051 , H01L2224/06181 , H01L2224/06517 , H01L2224/08145 , H01L2224/08146 , H01L2224/80379 , H01L2924/04941 , H01L2924/04953 , H01L2924/0496 , H01L2924/0504 , H01L2924/0509 , H01L2924/0544 , H01L2924/059 , H01L2924/30105
摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.
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公开(公告)号：US20240120304A1
公开(公告)日：2024-04-11
申请号：US17993905
申请日：2022-11-24
申请人： Innolux Corporation
发明人： Tzu-Sheng Wu , Haw-Kuen Liu , Chung-Jyh Lin , Cheng-Chi Wang , Wen-Hsiang Liao , Te-Hsun Lin
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/17 , H01L25/16 , H01L2224/034 , H01L2224/0362 , H01L2224/05005 , H01L2224/05017 , H01L2224/05018 , H01L2224/05082 , H01L2224/05541 , H01L2224/05557 , H01L2224/05558 , H01L2224/05573 , H01L2224/0603 , H01L2224/13005 , H01L2224/13082 , H01L2224/16148 , H01L2224/16225 , H01L2224/16265 , H01L2224/17163 , H01L2924/19041 , H01L2924/19043
摘要： The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.
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公开(公告)号：US20240079392A1
公开(公告)日：2024-03-07
申请号：US18152740
申请日：2023-01-10
发明人： Chuei-Tang WANG , Tso-Jung Chang , Jeng-Shien Hsieh , Shih-Ping Lin , Chih-Peng Lin , Chieh-Yen Chen , Chen-Hua Yu
CPC分类号： H01L25/105 , H01L21/561 , H01L21/568 , H01L23/5383 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/20 , H01L24/24 , H01L24/80 , H01L25/50 , H10B80/00 , H01L24/09 , H01L2224/05018 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05562 , H01L2224/05571 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/08235 , H01L2224/08237 , H01L2224/09181 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16227 , H01L2224/214 , H01L2224/215 , H01L2224/24137 , H01L2224/244 , H01L2224/245 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2225/1023 , H01L2225/107 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/014
摘要： A semiconductor structure includes a first tier, a redistribution circuit structure, and a second tier. The first tier includes at least one first die. The redistribution circuit structure is disposed on the first tier and electrically coupled to the at least one first die, where the redistribution circuit structure has a multi-layer structure and includes a vertical connection structure continuously extending from a first side of the redistribution circuit structure to a second side of the redistribution circuit structure, and the first side is opposite to the second side along a stacking direction of the first tier and the redistribution circuit structure. The second tier includes a plurality of second dies, and is disposed on and electrically coupled to the redistribution circuit structure. The redistribution circuit structure is disposed between the first tier and the second tier, where the at least one first die is electrically connected to and electrically communicated with the plurality of second dies through the redistribution circuit structure, and the plurality of second dies are electrically connected to and electrically communicated with each other through the redistribution circuit structure.
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公开(公告)号：US20240038694A1
公开(公告)日：2024-02-01
申请号：US18076210
申请日：2022-12-06
申请人： Celestial AI Inc.
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48
CPC分类号： H01L24/02 , H01L21/76898 , H01L23/481 , H01L24/05 , H01L24/13 , H01L2224/02313 , H01L2224/02331 , H01L2224/02372 , H01L2224/02381 , H01L2224/05548 , H01L2224/05655 , H01L2224/05644 , H01L2224/05569 , H01L2224/05008 , H01L2224/05082 , H01L2224/05025 , H01L2224/05018 , H01L2224/05559 , H01L2224/13155 , H01L2224/13144 , H01L2224/13147 , H01L2224/13024 , H01L2224/13021
摘要： A method is described. The method includes creating a partial through-substrate via (TSV) plug in a front side of a wafer, the partial TSV having a front side and a back side. The back side of the partial TSV extending toward a front side of a substrate but not into a bulk of the substrate. A cavity is etched in a back side of the wafer that exposes the partial TSV plug. An insulator is applied to the etched back side of the wafer. A portion of the partial TSV plug is exposed by removing a portion of the insulator. A conductive material is deposited to connect the exposed, partial TSV plug to a surface on the back side of the wafer.
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公开(公告)号：US20230411323A1
公开(公告)日：2023-12-21
申请号：US18188781
申请日：2023-03-23
发明人： Etsuko WATANABE , Takashi TONEGAWA
IPC分类号： H01L23/00
CPC分类号： H01L24/06 , H01L23/49513 , H01L24/40 , H01L24/48 , H01L24/05 , H01L24/73 , H01L24/03 , H01L2924/13055 , H01L2924/13091 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/06051 , H01L2224/06181 , H01L2224/06505 , H01L2224/06102 , H01L2224/05018 , H01L2224/05027 , H01L2224/05166 , H01L2224/05184 , H01L2924/0132 , H01L2224/05186 , H01L2924/04941 , H01L2224/05124 , H01L2224/05138 , H01L2924/01014 , H01L2224/05147 , H01L2924/0133 , H01L2224/05155 , H01L2224/05083 , H01L2224/05084 , H01L2224/05644 , H01L2224/05624 , H01L2224/05638 , H01L2224/05647 , H01L2224/05664 , H01L2224/05118 , H01L2224/05567 , H01L2224/03464 , H01L2224/48245 , H01L2224/48091 , H01L2224/37147 , H01L2224/37139 , H01L2224/40245 , H01L24/29 , H01L2224/29139 , H01L24/32 , H01L2224/32245 , H01L2224/73221 , H01L2224/73265 , H01L2224/73263 , H01L24/37
摘要： A dielectric layer has a first opening exposing a surface of a first conductive layer and a second opening exposing a surface of a second conductive layer and having an opening area smaller than an opening area of the first opening. A material of the surface of the second conductive layer exposed from the second opening is different from a material of the surface of the first conductive layer exposed from the first opening, and includes aluminum.
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公开(公告)号：US20230389339A1
公开(公告)日：2023-11-30
申请号：US18169839
申请日：2023-02-15
发明人： Chao LIN
CPC分类号： H10B80/00 , H01L24/02 , H01L24/80 , H01L24/06 , H01L24/05 , H01L24/08 , H01L2224/0231 , H01L2224/02373 , H01L2224/02381 , H01L2224/02375 , H01L2224/0239 , H01L2924/01029 , H01L2924/01013 , H01L2924/0132 , H01L2924/01074 , H01L2224/05018 , H01L2224/05026 , H01L2224/05166 , H01L2224/05184 , H01L2224/05181 , H01L2224/05169 , H01L2224/05186 , H01L2924/04941 , H01L2224/05647 , H01L2224/05624 , H01L2224/05684 , H01L2224/05571 , H01L2224/80357 , H01L2224/8001 , H01L2224/80895 , H01L2224/06158 , H01L2224/08145 , H01L2924/1431 , H01L2924/1436
摘要： A semiconductor structure includes a first semiconductor layer and a second semiconductor layer bonded to each other. The first semiconductor layer includes a first redistribution line, and the first redistribution line has a first projection length on a bonding surface of the first semiconductor layer and the second semiconductor layer. The second semiconductor layer includes a second redistribution line, and the second redistribution line has a second projection length on the bonding surface. The first projection length is different from the second projection length. The first redistribution line is electrically connected to the second redistribution line. A method for forming the same is also provided.
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公开(公告)号：US11830832B2
公开(公告)日：2023-11-28
申请号：US17207028
申请日：2021-03-19
发明人： Tung-Jiun Wu , Mingni Chang , Ming-Yih Wang , Yinlung Lu
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0226 , H01L2224/02235 , H01L2224/02251 , H01L2224/02255 , H01L2224/03614 , H01L2224/0401 , H01L2224/05018 , H01L2224/13026 , H01L2224/13147 , H01L2924/07025 , H01L2924/3512
摘要： A semiconductor structure is provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure over the dielectric surface. A first protecting structure over the passivation layer. A conductive pad over the dielectric surface. A polymer layer over the first protecting structure and the conductive pad. A conductive bump electrically coupled to the conductive pad through an opening of the polymer layer. A first portion of the first protecting structure is leveled with the conductive pad and a second portion of the first protecting structure is higher than the conductive pad.
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9.发明公开公开(公告)号：US20230299026A1
公开(公告)日：2023-09-21
申请号：US17947324
申请日：2022-09-19
发明人： Myungho PARK , Heejin Park , Beomsu KIM
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L24/13 , H01L24/29 , H01L24/03 , H01L2924/35121 , H01L2924/3511 , H01L2924/30101 , H01L2924/13091 , H01L2224/13147 , H01L2224/13144 , H01L2224/13155 , H01L2224/13083 , H01L2224/13019 , H01L2224/29007 , H01L2224/29019 , H01L2224/29083 , H01L2224/29147 , H01L2224/29144 , H01L2224/29155 , H01L2224/13007 , H01L2224/05666 , H01L2224/05684 , H01L2224/05576 , H01L2224/05691 , H01L2224/05541 , H01L2224/05557 , H01L2224/05558 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/05124 , H01L2224/05084 , H01L2224/05017 , H01L2224/05018 , H01L2224/05005 , H01L2224/0345 , H01L2224/03614 , H01L2224/03622
摘要： A wafer level chip scale package includes a semiconductor substrate having a first thickness, an input-output pad formed on the semiconductor substrate, a front metal layer having a second thickness formed on the input-output pad, a back metal layer having a third thickness formed on a bottom of the semiconductor substrate, and a metal bump formed on the semiconductor substrate.
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公开(公告)号：US20230230944A1
公开(公告)日：2023-07-20
申请号：US17959352
申请日：2022-10-04
发明人： Boin NOH , Jeong Hoon AHN , Yun Ki CHOI
IPC分类号： H01L23/00 , H01L25/065
CPC分类号： H01L24/05 , H01L25/0657 , H01L24/32 , H01L24/73 , H01L24/08 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06565 , H01L24/16 , H01L2224/16227 , H01L2224/73204 , H01L2224/32145 , H01L2224/32225 , H01L2924/3511 , H01L2924/1434 , H01L2924/1431 , H01L2224/73253 , H01L2224/08148 , H01L2224/05655 , H01L2224/05541 , H01L2224/05554 , H01L2224/05555 , H01L2224/05557 , H01L2224/05558 , H01L2224/05573 , H01L2224/05009 , H01L2224/05017 , H01L2224/05018 , H01L2224/05073 , H01L2224/05082 , H01L2224/05155 , H01L2224/05166
摘要： A semiconductor package includes a second semiconductor chip disposed on a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate, a through via, and a lower pad disposed on the through via. The lower pad includes a first segment and a second segment connected thereto. The first segment overlaps the through via. The second segment is disposed on an edge region of the first segment. The second segment has an annular shape. The second semiconductor chip includes a second semiconductor substrate, an upper pad disposed on a bottom surface of the second semiconductor substrate, and a connection terminal disposed between the upper and lower pads. The second segment at least partially surrounds a lateral surface of the upper pad. A level of a top surface of the second segment is higher than that of an uppermost portion of the connection terminal.
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