公开(公告)号：US09123806B2

公开(公告)日：2015-09-01

申请号：US14282946

申请日：2014-05-20

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Joachim Mahler

IPC: H01L29/78 ,  H01L23/31 ,  H01L29/06 ,  H01L29/66 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L29/7827 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3185 ,  H01L24/05 ,  H01L29/0657 ,  H01L29/66666 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: The method includes providing a semiconductor chip having a first main face and a second main face opposite the first main face. The semiconductor chip includes an electrical device adjacent to the first main face. Material of the semiconductor chip is removed at the second main face except for a pre-defined portion so that a non-planar surface remains at the second main face.

Abstract translation: 该方法包括提供具有第一主面和与第一主面相对的第二主面的半导体芯片。 半导体芯片包括与第一主面相邻的电气装置。 除了预定义的部分之外，在第二主面处除去半导体芯片的材料，使得非平面表面保留在第二主面。

公开(公告)号：US09082767B2

公开(公告)日：2015-07-14

申请号：US14151917

申请日：2014-01-10

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/48 ,  H01L23/28 ,  H01L21/58 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00

Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

Abstract translation: 提供一种嵌入式集成电路封装，所述嵌入式集成电路封装包括：至少一个布置在芯片载体上的芯片，所述至少一个芯片包括多个芯片接触焊盘; 形成在所述芯片载体上并且至少部分地围绕所述至少一个芯片的封装材料; 通过所述封装材料形成的多个电互连，其中每个电互连电连接到芯片接触焊盘; 以及形成在嵌入式集成电路封装的电互连之间的结构，其中该结构增加了电互连之间的耐爬电阻性。

公开(公告)号：US20150111343A1

公开(公告)日：2015-04-23

申请号：US14581653

申请日：2014-12-23

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Klaus Schmidt ,  Franz-Peter Kalz

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/00 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/26165 ,  H01L2224/27462 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82345 ,  H01L2224/82385 ,  H01L2224/82986 ,  H01L2224/831 ,  H01L2224/83851 ,  H01L2224/92144 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

Abstract translation: 电子部件包括导电载体。 导电载体包括载体表面，半导体芯片包括芯片表面。 载体表面和芯片表面中的一个或两个包括非平面结构。 芯片附着到载体上，其芯片表面面向载体表面，使得由于载体表面和第一芯片表面之一或两者的非平面结构，在芯片表面和载体表面之间提供间隙 。 电子部件还包括位于间隙中的第一电沉积金属层。

公开(公告)号：US20150076672A1

公开(公告)日：2015-03-19

申请号：US14028577

申请日：2013-09-17

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Franz-Peter Kalz ,  Joachim Voelter ,  Ralf Wombacher

IPC: H01L23/00 ,  H01L23/495

CPC classification number: H01L25/0655 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/492 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83095 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/83

Abstract: A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Abstract translation: 提供了一种制造芯片封装的方法。 该方法可以包括电接触至少一个第一芯片，第一芯片包括第一侧和与第一侧相对的第二侧，其第二侧为导电载体。 绝缘层形成在导电载体的至少一部分上并且在芯片的第一侧的至少一部分上方。 至少一个第二芯片布置在绝缘层上。 在第一芯片和第二芯片上形成封装材料。 电触头通过封装材料形成至少一个第一芯片和至少一个第二芯片的至少一个触点的至少一个触点。

公开(公告)号：US20150064844A1

公开(公告)日：2015-03-05

申请号：US14543557

申请日：2014-11-17

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Thomas Bemmerl ,  Anton Prueckl

IPC: H01L21/768 ,  H01L25/00

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/224 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24105 ,  H01L2224/24155 ,  H01L2224/24175 ,  H01L2224/244 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/35 ,  H01L2224/352 ,  H01L2224/3701 ,  H01L2224/37113 ,  H01L2224/37118 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/37164 ,  H01L2224/37169 ,  H01L2224/40095 ,  H01L2224/40155 ,  H01L2224/40175 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/41171 ,  H01L2224/48155 ,  H01L2224/48175 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82104 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84447 ,  H01L2224/92244 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01049 ,  H01L2924/01014 ,  H01L2924/07811 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01023 ,  H01L2224/45099

Abstract: An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor.

Abstract translation: 电子设备包括与第一芯片载体隔离的第一芯片载体和第二芯片载体。 第一功率半导体芯片安装在电连接到第一芯片载体上。 第二功率半导体芯片安装在第二芯片载体上并电连接到第二芯片载体。 电绝缘材料被配置为至少部分地围绕第一功率半导体芯片和第二功率半导体芯片。 电互连被配置为将第一功率半导体芯片电连接到第二功率半导体芯片，其中电互连具有接触夹和电沉积导体中的至少一个。

公开(公告)号：US20150028448A1

公开(公告)日：2015-01-29

申请号：US13951556

申请日：2013-07-26

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Georg Meyer-Berg

IPC: H01L25/065 ,  H01L23/12 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/492 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/85 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L28/00 ,  H01L2224/04105 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/16265 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/24265 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/85 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/0105 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A chip package includes an electrically conducting chip carrier and at least one first semiconductor chip attached to the electrically conducting chip carrier. The chip package further includes a passive component. The electrically conducting chip carrier, the at least one first semiconductor chip, and the passive component are embedded in an insulating laminate structure.

Abstract translation: 芯片封装包括导电芯片载体和连接到导电芯片载体的至少一个第一半导体芯片。 芯片封装进一步包括无源元件。 导电芯片载体，至少一个第一半导体芯片和无源部件被嵌入绝缘层压结构中。

公开(公告)号：US20140197527A1

公开(公告)日：2014-07-17

申请号：US13742455

申请日：2013-01-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini ,  Franz-Peter Kalz

IPC: H01L23/495 ,  H01L21/77

CPC classification number: H01L21/4807 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/77 ,  H01L23/3731 ,  H01L23/3735 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49586 ,  H01L24/27 ,  H01L24/743 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%.

Abstract translation: 提供了芯片布置，芯片布置包括载体; 电连接到所述载体的第一芯片; 布置在所述载体上的陶瓷层; 以及设置在所述陶瓷层上的第二芯片; 其中所述陶瓷层的孔隙率在约3％至约70％的范围内。

公开(公告)号：US20140021634A1

公开(公告)日：2014-01-23

申请号：US13944595

申请日：2013-07-17

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Joachim Mahler

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/492 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/80 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/83

Abstract: A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.

Abstract translation: 一种方法包括提供具有第一空腔的载体，提供具有附着到电介质箔的金属层的电介质箔，将第一半导体芯片放置在载体的第一腔中，以及将电介质箔施加到载体上。

公开(公告)号：US20130277704A1

公开(公告)日：2013-10-24

申请号：US13921060

申请日：2013-06-18

Applicant: Infineon Technologies AG

Inventor： Andreas Eder ,  Henrik Ewe ,  Stefan Landau ,  Joachim Mahler

IPC: H01L33/56

CPC classification number: H01L33/56 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2933/0066 ,  H01L2224/82 ,  H01L2924/00

Abstract: A method and a system for a reliable LED semiconductor device are provided. In one embodiment, the device comprises a carrier, a light emitting diode disposed on the carrier, an encapsulating material disposed over the light emitting diode and the carrier, at least one through connection formed in the encapsulating material, and a metallization layer disposed and structured over the at least one through connection.

Abstract translation: 提供了一种可靠的LED半导体器件的方法和系统。 在一个实施例中，该装置包括载体，设置在载体上的发光二极管，设置在发光二极管和载体上的封装材料，形成在封装材料中的至少一个贯穿连接，以及设置和结构化的金属化层 通过至少一个通过连接。