公开(公告)号：US08816407B2

公开(公告)日：2014-08-26

申请号：US13765696

申请日：2013-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-yeon Kim ,  Tae-hong Min ,  Yeong-kwon Ko ,  Tae-je Cho

IPC: H01L23/48 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/3135 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: Semiconductor packages are disclosed. A semiconductor package includes: a first chip that includes a chip region and scribe regions at edges of the chip region, wherein the chip region comprises integrated circuit units and main through substrate vias electrically connected to the integrated circuit units; and a second chip that is bonded onto the first chip. The semiconductor package includes dummy conductive connectors including at least dummy wiring lines, the dummy conductive connectors electrically connected to the main through substrate vias at one end, and not capable of forming an electrical connection at the other end.

Abstract translation: 公开了半导体封装。 半导体封装包括：第一芯片，其在芯片区域的边缘处包括芯片区域和划线区域，其中芯片区域包括电连接到集成电路单元的集成电路单元和主通孔衬底通孔; 以及接合到第一芯片上的第二芯片。 半导体封装包括至少包括虚拟布线的虚拟导电连接器，虚拟导电连接器在一端电连接到主通孔衬底通孔，而不能在另一端形成电连接。

公开(公告)号：US09482584B2

公开(公告)日：2016-11-01

申请号：US13776973

申请日：2013-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-hyeok Im ,  Kyol Park ,  Tae-je Cho

IPC: G01K7/00 ,  G01K7/34 ,  G01K7/16 ,  G01K7/42

CPC classification number: G01K7/34 ,  G01K7/16 ,  G01K7/42

Abstract: A method of predicting a temperature includes operatively coupling a temperature prediction circuit to a device including a semiconductor chip, determining a correlation between a current and voltage of the temperature prediction circuit, and predicting a temperature with respect to power applied to the device using the determined correlation.

Abstract translation: 预测温度的方法包括将温度预测电路可操作地耦合到包括半导体芯片的装置，确定温度预测电路的电流和电压之间的相关性，以及使用所确定的温度预测相对于施加到装置的功率的温度 相关性。

公开(公告)号：US09412707B2

公开(公告)日：2016-08-09

申请号：US14702662

申请日：2015-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-soo Chung ,  Tae-je Cho ,  Jung-seok Ahn ,  In-young Lee

IPC: H01L29/40 ,  H01L23/00 ,  H01L23/48 ,  H01L21/78 ,  H01L21/304 ,  H01L21/683 ,  H01L25/00 ,  H01L25/065 ,  H01L21/768 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/4803 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.

Abstract translation: 本发明的实施例包括一种制造半导体封装的方法，该半导体封装包括多个层叠半导体芯片，其中半导体封装在晶片级制造时可以防止半导体晶片衬底的边缘损坏或破裂，而直径 的模制元件的直径大于半导体晶片衬底的直径。 成型元件可以覆盖晶片基板的表面和多个堆叠的半导体芯片。 实施例可以包括晶片级半导体封装，其包括具有第一直径的圆形衬底，附着到圆形衬底的圆形钝化层，具有第一直径的钝化层和覆盖多个半导体芯片的表面的圆形模制元件，以及 覆盖基板的有效区域。 圆形模制元件可以具有大于第一直径的第二直径。

公开(公告)号：US09070729B2

公开(公告)日：2015-06-30

申请号：US14497382

申请日：2014-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-wook Ji ,  Hyoung-yol Mun ,  Yeong-Iyeol Park ,  Tae-je Cho

IPC: H01L21/683 ,  H01L21/304 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/6835 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/304 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2223/54493 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer processing method, by which a device wafer may be aligned and bonded to a carrier wafer to perform a back grinding process for the device wafer and may be separated from the carrier wafer after performing the back grinding process, and a method of manufacturing a semiconductor device by using the wafer processing method are provided. The wafer processing method includes: disposing a first magnetic material on a front side of a wafer and disposing a second magnetic material on a carrier wafer, wherein a surface of the first magnetic material and a surface of the second magnetic material, which face each other, have opposite polarities; aligning and bonding the wafer to the carrier wafer by magnetic attraction between the first magnetic material and the second magnetic material; grinding a back side of the wafer to make the wafer thin; and separating the wafer from the carrier wafer.

Abstract translation: 一种晶片处理方法，通过该晶圆处理方法，可以将器件晶片对准并结合到载体晶片以对器件晶片进行背面磨削处理，并且可以在执行背面磨削工艺之后与载体晶片分离，并且制造 提供了使用晶片处理方法的半导体器件。 晶片处理方法包括：将第一磁性材料设置在晶片的前侧，并在载体晶片上设置第二磁性材料，其中第一磁性材料的表面和第二磁性材料的表面彼此面对 ，具有相反的极性; 通过第一磁性材料和第二磁性材料之间的磁吸引将晶片对准和结合到载体晶片; 研磨晶片的背面以使晶片变薄; 以及将晶片与载体晶片分离。

公开(公告)号：US08847378B2

公开(公告)日：2014-09-30

申请号：US13738322

申请日：2013-01-10

Applicant: Samsung Electronics Co., Ltd

Inventor： Yun-Seok Choi ,  Tae-je Cho

IPC: H01L23/02 ,  H01L23/48 ,  H01L25/10 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11

Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip.

Abstract translation: 半导体封装包括第一半导体封装，第二半导体封装和封装连接元件。 第一半导体封装包括第一衬底，设置在第一衬底上并包括多个第一半导体芯片的芯片堆叠部分，以及用于围绕第一衬底上的芯片堆叠部分的第一密封剂。 第二半导体封装包括第二衬底，设置在第二衬底上的至少一个第二半导体芯片和用于围绕第二衬底上的第二半导体芯片的第二密封剂。 封装连接部件电连接第一半导体封装和第二半导体封装。 多个第一半导体芯片包括通过硅通孔（TSV）的第一芯片和通过TSV与第一芯片电连接的第二芯片，并且芯片堆叠部分包括用于填充第一芯片和第二芯片之间的空间的内部密封剂 第二芯片并且延伸到第二芯片的一侧。

公开(公告)号：US10008462B2

公开(公告)日：2018-06-26

申请号：US15226231

申请日：2016-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Tae-je Cho ,  Yong-hwan Kwon ,  Hyung-gil Baek ,  Hyun-soo Chung ,  Seung-kwan Ryu ,  Myeong-soon Park

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L24/08 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/08058 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/19105 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/034 ,  H01L2224/1146 ,  H01L2224/0361 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01024 ,  H01L2924/01022

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

公开(公告)号：US09831202B2

公开(公告)日：2017-11-28

申请号：US15262040

申请日：2016-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Seung-kwan Ryu ,  Ju-il Choi ,  Tae-je Cho ,  Yong-hwan Kwon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13076 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13564 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section.

公开(公告)号：US09761477B2

公开(公告)日：2017-09-12

申请号：US15286801

申请日：2016-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gun-ho Chang ,  Un-byoung Kang ,  Tae-je Cho

IPC: H01L21/78 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/36 ,  H01L21/768 ,  H01L21/304 ,  H01L23/544

CPC classification number: H01L21/6836 ,  H01L21/304 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/36 ,  H01L23/544 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/5446 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/11002 ,  H01L2224/11009 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/1362 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13664 ,  H01L2224/14519 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17181 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/18161

Abstract: Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

公开(公告)号：US09728424B2

公开(公告)日：2017-08-08

申请号：US14723642

申请日：2015-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hwang Kim ,  Un-byoung Kang ,  Cha-jea Jo ,  Tae-je Cho

IPC: H01L21/00 ,  H01L23/48 ,  B23K31/02 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L23/14

CPC classification number: H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor package includes forming a bonding layer on a carrier substrate, bonding an inner substrate to the carrier substrate, removing the carrier substrate, and forming a gap-filling portion by removing a portion of the bonding layer to expose a portion of a solder ball provided in the inner substrate. The inner substrate may be mounted on a package substrate and a semiconductor chip may be mounted on the inner substrate.

公开(公告)号：US20170084558A1

公开(公告)日：2017-03-23

申请号：US15226231

申请日：2016-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Tae-je Cho ,  Yong-hwan Kwon ,  Hyung-gil Baek ,  Hyun-soo Chung ,  Seung-kwan Ryu ,  Myeong-soon Park

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L24/08 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/08058 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/19105 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/034 ,  H01L2224/1146 ,  H01L2224/0361 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01024 ,  H01L2924/01022

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.