Patent search ap:("TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Page LTD.") AND inv:"Cheng-Chung Lin"

11.

发明授权
System and method of timing characterization for semiconductor circuit 有权

公开(公告)号：US10824784B2

公开(公告)日：2020-11-03

申请号：US16578989

申请日：2019-09-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chia Hao Tu , Hsueh-Chih Chou , Sang Hoo Dhong , Jerry Chang Jui Kao , Chi-Lin Liu , Cheng-Chung Lin , Shang-Chih Hsieh

IPC: G06F30/3312 , G06F1/14

Abstract: A method is provided. A library associated with a cell is received. A minimum setup time of the cell is acquired in response to an ideal hold time according to the library and a reference clock. A maximum hold time of the cell is acquired in response to the minimum setup time according to the library and the reference clock. A plurality of candidate hold times are determined. A plurality of candidate setup times are acquired corresponding to the plurality of candidate hold times according to the library and the reference clock. The plurality of candidate setup times are added to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows. A target time window is selected that has a minimal time span among the candidate time windows.

12.

发明授权
Electron beam lithography methods including time division multiplex loading 有权
Title translation: 电子束光刻方法，包括时分复用加载

公开(公告)号：US09378926B2

公开(公告)日：2016-06-28

申请号：US14604488

申请日：2015-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Zhang Kuo , Ping-Lin Yang , Cheng-Chung Lin , Osamu Takahashi , Sang Hoo Dhong

IPC: G21K5/04 , H01J37/317 , H01J37/302

CPC classification number: H01J37/3175 , H01J37/3023 , H01J37/3177 , H01J2237/2485 , H01J2237/31762

Abstract: An embodiment of a method of lithography includes generating a beam of electrons. A first pixel and a second pixel are each configured to pattern the beam. Using time domain multiplex loading, the first and second pixels are controlled such that the beam is patterned. The patterning includes receiving a first clock signal and using the first clock signal to generate a second clock signal and a third clock signal. The second clock signal is sent to the first pixel and sending the third clock signal is sent to the second pixel.

Abstract translation: 光刻方法的一个实施例包括产生电子束。第一像素和第二像素都被配置为对光束进行图案化。使用时域多路复用加载，控制第一和第二像素使得光束被图案化。图案化包括接收第一时钟信号并使用第一时钟信号来产生第二时钟信号和第三时钟信号。第二时钟信号被发送到第一像素，并且发送第三时钟信号被发送到第二像素。

13.

发明授权
Method of making a conductive pillar bump with non-metal sidewall protection structure 有权
Title translation: 制造具有非金属侧壁保护结构的导电柱凸块的方法

公开(公告)号：US09287171B2

公开(公告)日：2016-03-15

申请号：US14444759

申请日：2014-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yi-Wen Wu , Cheng-Chung Lin , Chien Ling Hwang , Chung-Shi Liu

IPC: H01L21/44 , H01L21/768 , H01L23/498 , H01L23/00

CPC classification number: H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0345 , H01L2224/0401 , H01L2224/05023 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05541 , H01L2224/05568 , H01L2224/05582 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05681 , H01L2224/05687 , H01L2224/10145 , H01L2224/11002 , H01L2224/1112 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11827 , H01L2224/11831 , H01L2224/11849 , H01L2224/11912 , H01L2224/13005 , H01L2224/13007 , H01L2224/13023 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13118 , H01L2224/1312 , H01L2224/13123 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/1317 , H01L2224/13171 , H01L2224/13181 , H01L2224/13551 , H01L2224/13561 , H01L2224/13565 , H01L2224/1357 , H01L2224/1358 , H01L2224/13582 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13664 , H01L2224/13686 , H01L2224/13687 , H01L2224/13688 , H01L2224/1369 , H01L2224/81192 , H01L2224/81193 , H01L2224/814 , H01L2224/81815 , H01L2224/94 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/05442 , H01L2924/0665 , H01L2924/07025 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/3841 , H01L2924/0105 , H01L2224/11 , H01L2924/01007 , H01L2924/01014 , H01L2924/01015 , H01L2924/00 , H01L2224/05552

Abstract: A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.

Abstract translation: 制造半导体器件的方法包括在衬底上形成凸块下金属（UBM）层，UBM层包括侧壁和表面区域。所述方法还包括在所述UBM层上形成导电柱，所述导电柱包括侧壁，其中所述导电柱暴露所述UBM层的表面区域。所述方法还包括在所述导电柱的侧壁上形成非金属保护结构，其中所述非金属保护结构接触所述UBM层的表面区域，并且所述非金属保护结构暴露所述UBM层的侧壁。

14.

发明授权
System and method for fine pitch PoP structure 有权
Title translation: 细间距PoP结构的系统和方法

公开(公告)号：US09281288B2

公开(公告)日：2016-03-08

申请号：US14175668

申请日：2014-02-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chung Lin , Hsiu-Jen Lin , Cheng-Ting Chen , Chun-Cheng Lin , Ming-Da Cheng , Chung-Shi Liu

IPC: H01L23/00 , H01L23/498 , H01L25/10 , H01L25/00 , H01L23/538

CPC classification number: H01L24/14 , H01L23/49816 , H01L23/5389 , H01L25/105 , H01L25/50 , H01L2224/16225 , H01L2225/1023 , H01L2225/1058 , H01L2924/01322 , H01L2924/15311 , H01L2924/15331 , H01L2924/15787 , H01L2924/181 , H01L2924/18161 , H01L2924/00

Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Abstract translation: 提供了一种精细节距封装（PoP）和一种形成方法。 PoP可以通过将连接例如焊球放置在具有附接到其上的半导体管芯的第一基板上而形成。执行第一回流处理以延长焊球。此后，具有安装有另一个半导体管芯的第二基板连接到焊球。执行第二回流处理以形成沙漏连接。

15.

发明申请
MEMORY CIRCUIT FOR PRE-CHARGING AND WRITE DRIVING 有权
Title translation: 用于预充电和写入驱动的存储器电路

公开(公告)号：US20160012881A1

公开(公告)日：2016-01-14

申请号：US14326124

申请日：2014-07-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Zhang Kuo , Cheng-Chung Lin , Ho-Chieh Hsieh , Kuo Feng Tseng , Sang Hoo Dhong

IPC: G11C11/419 , G11C5/14

CPC classification number: G11C11/419 , G11C5/025 , G11C5/06 , G11C5/148 , G11C7/08 , G11C7/12 , G11C11/4076 , G11C11/4094 , G11C11/417

Abstract: A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized.

Abstract translation: 存储器包括字线，位线和互补位线。存储器单元具有耦合到位线的数据节点和耦合到互补位线的互补数据节点。字线控制对存储单元的访问。电路耦合到位线和互补位线。该电路被配置为基于预充电的第一定时和写入驱动的第二定时上拉至高电压，下拉至低电压或浮动位线和互补位线。第一定时和第二定时同步。

16.

发明申请
Pillar Bumps and Process for Making Same 有权
Title translation: 支柱碰撞和制作相同的过程

公开(公告)号：US20140363966A1

公开(公告)日：2014-12-11

申请号：US14468236

申请日：2014-08-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Chung Lin , Chung-Shi Liu , Meng-Wei Chou , Kuo Cheng Lin , Wen-Hsiung Lu , Chien Ling Hwang , Ying-Jui Huang , De-Yuan Lu

IPC: H01L23/00

CPC classification number: H01L24/11 , H01L21/02052 , H01L21/32125 , H01L21/76873 , H01L21/76885 , H01L23/488 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2221/1084 , H01L2224/03912 , H01L2224/0401 , H01L2224/05073 , H01L2224/05541 , H01L2224/05573 , H01L2224/1111 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/11472 , H01L2224/11474 , H01L2224/11614 , H01L2224/1181 , H01L2224/11849 , H01L2224/11903 , H01L2224/1191 , H01L2224/11912 , H01L2224/13005 , H01L2224/13017 , H01L2224/13018 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/81191 , H01L2924/00013 , H01L2924/01006 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01059 , H01L2924/01072 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0541 , H01L2924/07025 , H01L2924/10329 , H01L2924/14 , H01L2924/20102 , H01L2924/3512 , H01L2924/381 , H01L2924/3841 , H01L2924/0105 , H01L2924/00014 , H01L2224/13099 , H01L2924/207

Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.

Abstract translation: 用于提供焊料柱凸块的装置和方法。通过在集成电路的端子上通过导电材料的电镀形成导电材料的支柱，在集成电路的输入/输出端子上形成支柱凸点连接。柱状凸块的基部具有比上部更大的宽度。柱形凸起的基部的横截面可以形成梯形，矩形或倾斜的形状。焊料可以形成在柱的顶表面上。所得到的焊料柱凸起形成比现有技术更可靠的细间距封装焊接连接。

17.

发明申请
Charged Particle Lithography System With a Long Shape Illumination Beam 有权
Title translation: 带有长形照明光束的带电粒子光刻系统

公开(公告)号：US20140212815A1

公开(公告)日：2014-07-31

申请号：US13756178

申请日：2013-01-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jimmy Hsiao , Ming-Zhang Kuo , Ping-Lin Yang , Cheng-Chung Lin , Osamu Takahashi , Sang Hoo Dhong

IPC: H01J29/60 , H01J29/62

CPC classification number: H01J29/62 , H01J3/12 , H01J3/16 , H01J3/18 , H01J37/3007 , H01J37/3177 , H01J2237/1205 , H01J2237/31789

Abstract: A system includes an integrated circuit (IC) design data base having a feature, a source configured to generate a radiation beam, a pattern generator (PG) including a mirror array plate and an electrode plate disposed over the mirror array plate, wherein the electrode plate includes a lens let having a first dimension and a second dimension perpendicular to the first dimension with the first dimension larger than the second dimension so that the lens let modifies the radiation beam to form the long shaped radiation beam, and a stage configured secured the substrate. The system further includes an electric field generator connecting the minor array plate. The mirror array plate includes a mirror. The mirror absorbs or reflects the radiation beam. The radiation beam includes electron beam or ion beam. The second dimension is equal to a minimum dimension of the feature.

Abstract translation: 一种系统包括具有特征的集成电路（IC）设计数据库，被配置为产生辐射束的源，包括反射镜阵列板的图案发生器（PG）和设置在所述反射镜阵列板上的电极板，其中所述电极板包括透镜，其具有垂直于第一尺寸的第一尺寸和第二尺寸，其第一尺寸大于第二尺寸，使得透镜使得辐射束修改以形成长形辐射束，并且被配置为将基质。该系统还包括连接小阵列板的电场发生器。镜阵列板包括镜子。镜子吸收或反射辐射束。辐射束包括电子束或离子束。第二个维度等于该特征的最小尺寸。