公开(公告)号：US20140113446A1

公开(公告)日：2014-04-24

申请号：US14144906

申请日：2013-12-31

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/10145 ,  H01L2224/10175 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/27013 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/81097 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81208 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate.

Abstract translation: 半导体器件具有具有多个具有互连部位的多个导体迹线的多个管芯凸块焊盘和衬底的半导体管芯。 在芯片凸块焊盘或互连部位之间间隙地形成焊接掩模贴片。 导电凸块材料沉积在互连部位或模具凸块上。 将半导体管芯安装到衬底上，使得导电凸块材料设置在管芯凸块焊盘和互连部位之间。 导电凸块材料在管芯凸块焊盘或互连部位周围没有焊接掩模回流，以在半导体管芯和衬底之间形成互连结构。 焊接掩模贴片将导电凸块材料限制在管芯凸块焊盘或互连部位内。 互连结构可以包括可熔部分和不可熔部分。 密封剂沉积在半导体管芯和衬底之间。

公开(公告)号：US20140084415A1

公开(公告)日：2014-03-27

申请号：US14092304

申请日：2013-11-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kai Liu ,  Kang Chen

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1206 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/30107 ,  H03H2001/0078 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Abstract translation: 半导体器件具有第一半导体管芯。 在第一半导体管芯上形成第一电感器。 第二电感器形成在第一电感器上并与第一电感器对准。 在第一半导体管芯和第一和第二电感器上形成绝缘层。 导电桥形成在绝缘层之上并电连接在第二电感器和第一半导体管芯之间。 在一个实施例中，半导体器件具有第二半导体管芯，并且在第一和第二半导体管芯之间形成导电层。 在另一实施例中，在第一半导体管芯上形成电容器。 在另一个实施例中，绝缘层在第一半导体管芯的覆盖区之上具有第一厚度，并且第二厚度小于第一半导体管芯的覆盖区之外的第一厚度。

公开(公告)号：US20140077389A1

公开(公告)日：2014-03-20

申请号：US13800807

申请日：2013-03-13

Applicant: STATS CHIPPAC, LTD.

Inventor： Il Kwon Shim ,  Jun Mo Koo ,  Pandi C. Marimuthu ,  Yaojian Lin ,  See Chian Lim

IPC: H01L23/48 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01082 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts.

Abstract translation: 半导体器件具有包括基底和从基底延伸的多个导电柱的基底。 衬底可以是晶片形状，面板或单体形式。 导电柱可以具有圆形，矩形，锥形或变窄的中间形状。 通过导电柱之间的底座中的开口设置半导体管芯。 半导体管芯延伸到导电柱之上，或者设置在导电柱的下方。 密封剂沉积在半导体管芯上并且在导电柱周围。 去除基底和一部分密封剂以电绝缘导电柱。 在半导体管芯，密封剂和导电柱之上形成互连结构。 在半导体管芯，密封剂和导电柱上形成绝缘层。 半导体封装设置在半导体管芯上并电连接到导电柱。

公开(公告)号：US20140077381A1

公开(公告)日：2014-03-20

申请号：US14080609

申请日：2013-11-14

Applicant: STATS CHIPPAC, LTD.

Inventor： Yaojian Lin ,  Jose A. Caparas ,  Kang Chen ,  Hin Hwa Goh

IPC: H01L25/00 ,  H01L23/28 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/00 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73259 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.

Abstract translation: 半导体器件具有第一半导体管芯，其包括安装在具有热可释放层的载体上的TSV。 具有第一热膨胀系数CTE的第一密封剂沉积在第一半导体管芯上。 第一密封剂包括第一密封剂的周边中的升高部分，其减少翘曲。 暴露TSV的表面。 第二半导体管芯安装到TSV的表面，并在第一和第二半导体管芯之间形成间隙。 具有第二CTE的第二密封剂沉积在第一和第二半导体管芯上并且在间隙内。 第一个CTE大于第二个CTE。 在一个实施例中，第一和第二密封剂形成在追逐模具中。 在第一和第二半导体管芯上形成互连结构。

公开(公告)号：US20140077364A1

公开(公告)日：2014-03-20

申请号：US13832781

申请日：2013-03-15

Applicant: STATS CHIPPAC, LTD.

Inventor： Pandi C. Marimuthu ,  Sheila Marie L. Alvarez ,  Yaojian Lin ,  Jose A. Caparas ,  Yang Kern Jonathan Tan

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/2633 ,  H01L21/311 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/02311 ,  H01L2224/02379 ,  H01L2224/0558 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24227 ,  H01L2224/25171 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49174 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/821 ,  H01L2224/94 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

Abstract translation: 半导体器件具有设置在衬底的第一表面上的衬底和半导体管芯。 线柱附接到基底的第一表面。 线螺柱包括基部和杆部。 在衬底的第二表面上形成焊盘。 密封剂沉积在衬底，半导体管芯和线螺柱上。 密封剂的一部分被LDA去除以暴露线螺柱。 通过LDA去除一部分密封剂以暴露基底。 互连结构形成在密封剂上并电连接到线芯和半导体管芯。 在互连结构上形成凸点。 半导体封装设置在密封剂上并电连接到衬底。 分立半导体器件设置在密封剂上并电连接到衬底。

公开(公告)号：US20140070427A1

公开(公告)日：2014-03-13

申请号：US14082155

申请日：2013-11-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L24/96 ,  H01L25/0657 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/16225 ,  H01L2224/24 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/82 ,  H01L2224/821 ,  H01L2224/83 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2224/03 ,  H01L2224/80 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A semiconductor device has a plurality of semiconductor die mounted to a carrier. An encapsulant is deposited over the carrier around a peripheral region of the semiconductor die. A plurality of vias is formed through the encapsulant. A first conductive layer is conformally applied over a sidewall of the vias to form conductive vias. A second conductive layer is formed over a first surface of the semiconductor die between the conductive vias and contact pads of the semiconductor die. The first and second conductive layers can be formed during the same manufacturing process. A third conductive layer is formed over a second surface of the semiconductor die opposite the first surface of the semiconductor die. The third conductive layer is electrically connected to the conductive vias. A plurality of semiconductor die is stacked and electrically connected through the conductive vias and second and third conductive layers.

Abstract translation: 半导体器件具有安装到载体上的多个半导体管芯。 密封剂沉积在载体周围的半导体管芯的周边区域上。 通过密封剂形成多个通孔。 第一导电层保形地施加在通孔的侧壁上以形成导电通孔。 在半导体管芯的导电通孔和接触焊盘之间的半导体管芯的第一表面上形成第二导电层。 第一和第二导电层可以在相同的制造过程中形成。 在半导体管芯的与半导体管芯的第一表面相对的第二表面上形成第三导电层。 第三导电层电连接到导电通孔。 多个半导体管芯通过导电通孔和第二和第三导电层堆叠并电连接。

公开(公告)号：US20140070410A1

公开(公告)日：2014-03-13

申请号：US14084745

申请日：2013-11-20

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  JoonYoung Choi ,  WonIl Kwon

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05186 ,  H01L2224/0519 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00

Abstract: A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.

Abstract translation: 半导体晶片具有接触垫。 在晶片上形成第一绝缘层。 在第一绝缘层和接触垫上形成第二绝缘层。 去除第二绝缘层的一部分以露出接触垫。 第一UBM层形成在第二绝缘层和接触垫的轮廓之上并且跟随第二绝缘层和接触垫的轮廓以在接触垫上产生良好的孔。 在第一UBM层和接触垫上的阱中形成第一缓冲层。 在第一UBM层和第一缓冲层上形成第二UBM层。 在第二UBM层上形成第三UBM层。 在第三UBM层上形成凸块。 第一个缓冲层减少了凸块和接触垫上的应力。 可以在第二和第三UBM层之间形成第二缓冲层。

公开(公告)号：US20140008791A1

公开(公告)日：2014-01-09

申请号：US14021056

申请日：2013-09-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Pandi C. Marimuthu

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11822 ,  H01L2224/11906 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Abstract translation: 半导体器件具有半导体管芯，其具有形成在管芯上的第一导电层。 第一绝缘层形成在管芯上方，第一绝缘层中的第一开口布置在第一导电层上。 在第一绝缘层上形成第二导电层，并在第一导电层上形成第一导电层。 通过在第一绝缘层上形成第二绝缘层，其宽度小于第一开口的第二开口并将导电材料沉积到第二开口中来构造互连结构。 互连结构可以是导电柱或导电垫。 互连结构的宽度小于第一开口的宽度。 除去第一开口外部的第一绝缘层上的第二导电层，同时将第二导电层留在互连结构下。

公开(公告)号：US20140008769A1

公开(公告)日：2014-01-09

申请号：US14021206

申请日：2013-09-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L25/00

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/315 ,  H01L23/66 ,  H01L24/73 ,  H01L25/00 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.

Abstract translation: 半导体晶片具有多个具有应力敏感区域的第一半导体管芯。 掩模层或屏幕设置在应力敏感区域上方。 底部填充材料沉积在晶片上。 掩蔽层或屏幕防止邻近敏感区域形成底部填充材料。 去除掩模层或屏幕，留下邻近敏感区域的底部填充材料中的空腔。 将半导体晶片分割成第一模具。 第一管芯可以安装到堆积互连结构或第二半导体管芯，其中空腔分离敏感区域并建立互连结构或第二管芯。 在第一和第二管芯之间形成接合线，并且密封剂沉积在第一和第二管芯和接合线上。 可以通过第一或第二管芯形成导电通孔。

公开(公告)号：US20140004659A1

公开(公告)日：2014-01-02

申请号：US14020996

申请日：2013-09-09

Applicant: STATS ChipPAC, Ltd.

Inventor： SooMoon Park ,  ByoungWook Jang ,  DongSoo Moon

IPC: H01L21/54

CPC classification number: H01L21/54 ,  H01L21/563 ,  H01L24/743 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted over a surface of a substrate. A mold underfill dispensing needle has a width substantially equal to a width of the semiconductor die. The dispensing needle is placed in fluid communication with a side of the semiconductor die. A mold underfill is deposited from an outlet of the dispensing needle evenly across a width of the semiconductor die into an area between the semiconductor die and substrate without motion of the dispensing needle. The dispensing needle has a shank and the outlet in a T-configuration. The dispensing needle can have a plurality of pole portions between a shank and the outlet. The dispensing needle has a plate between a shank and the outlet. The outlet has an upper edge with a length substantially equal to or greater than a length of a lower edge of the outlet.

Abstract translation: 半导体器件具有安装在衬底的表面上的半导体管芯。 模具底部填充分配针的宽度基本上等于半导体管芯的宽度。 分配针与半导体管芯的一侧流体连通。 将分注针的出口从半导体管芯的宽度均匀地沉积到半导体管芯和衬底之间的区域中，而不会发生分配针的移动。 分配针具有柄和T形构件的出口。 分配针可以在柄和出口之间具有多个极部。 分配针具有在柄和出口之间的板。 出口具有长度基本上等于或大于出口下边缘长度的上边缘。