Abstract:
A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.
Abstract:
A method of forming a device includes performing a first plating process to form a first metallic feature, and performing an activation treatment to a surface of the first metallic feature in an activation treatment solution, wherein the activation treatment solution includes a treatment agent in de-ionized (DI) water. After the step of performing the activation treatment, performing a second plating process to form a second metallic feature and contacting the surface of the first metallic feature.
Abstract:
A method for fabricating bump structure forms an under-bump metallurgy (UBM) layer in an opening of an encapsulating layer, and then forms a bump layer on the UBM layer within the opening of the encapsulating layer. After removing excess material of the bump layer from the upper surface of the encapsulating layer, the encapsulating layer is removed till a top portion of the bump layer protrudes from the upper surface of the encapsulating layer.
Abstract:
The mechanism of forming a metal bump structure described above resolves the delamination issues between a conductive layer on a substrate and a metal bump connected to the conductive layer. The conductive layer can be a metal pad, a post passivation interconnect (PPI) layer, or a top metal layer. By performing an in-situ deposition of a protective conductive layer over the conductive layer (or base conductive layer), the under bump metallurgy (UBM) layer of the metal bump adheres better to the conductive layer and reduces the occurrence of interfacial delamination. In some embodiments, a copper diffusion barrier sub-layer in the UBM layer can be removed. In some other embodiments, the UBM layer is not needed if the metal bump is deposited by a non-plating process and the metal bump is not made of copper.
Abstract:
A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure.
Abstract:
A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.
Abstract:
A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a lengthwise direction. The second package component includes a metal pillar, wherein the second package component is disposed over the first package component. A solder region bonds the metal pillar to the metal trace, wherein the solder region contacts a top surface of the metal trace.
Abstract:
Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed.
Abstract:
Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint.
Abstract:
Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.