公开(公告)号：US20100155768A1

公开(公告)日：2010-06-24

申请号：US12714413

申请日：2010-02-26

Applicant: Charles W.C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

Inventor： Charles W.C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

IPC: H01L33/00

CPC classification number: H01L21/486 ,  H01L21/4882 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L33/483 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/32188 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15153 ,  H01L2924/16152 ,  H01L2924/19041 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/182 ,  H05K3/0061 ,  H05K2201/09054 ,  H05K2201/09745 ,  H05K2201/10106 ,  H01L2224/05599

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post and a base. The semiconductor device extends into a cavity in the post, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, and the base extends laterally from the post. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace is located outside the cavity and provides signal routing between a pad and a terminal.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线和粘合剂。 散热器包括一个柱子和一个底座。 半导体器件延伸到柱中的空腔中，电连接到导电迹线并且热连接到散热器。 柱从基部向上延伸到粘合剂中的开口中，并且基部从柱横向延伸。 粘合剂在柱和导电迹线之间以及基部和导电迹线之间延伸。 导电迹线位于腔体外部，并提供焊盘和端子之间的信号路由。

公开(公告)号：US20100033875A1

公开(公告)日：2010-02-11

申请号：US12458993

申请日：2009-07-29

Applicant: Yoshinari Yoshida ,  Hitoki Kanagawa

Inventor： Yoshinari Yoshida ,  Hitoki Kanagawa

IPC: G11B5/48

CPC classification number: G11B5/4833 ,  G11B5/486 ,  H05K1/021 ,  H05K1/056 ,  H05K2201/09745 ,  H05K2203/0369

Abstract: A suspension board with circuit includes a metal supporting board extending in a longitudinal direction, an insulating layer formed on the metal supporting board, and a conductive pattern formed on the insulating layer. In the suspension board with circuit, a magnetic-head mounting region where a slider with a magnetic head mounted thereon is mounted is located in one end portion in the longitudinal direction, and the thickness of the metal supporting board in at least a part of the magnetic-head mounting region is smaller than that in a region other than the magnetic-head mounting region.

Abstract translation: 具有电路的悬挂板包括沿纵向方向延伸的金属支撑板，形成在金属支撑板上的绝缘层，以及形成在绝缘层上的导电图案。 在具有电路的悬挂板中，安装有安装有磁头的滑块的磁头安装区域位于纵向方向的一个端部中，并且金属支撑板的至少一部分中的厚度 磁头安装区域小于磁头安装区域以外的区域。

公开(公告)号：US20090279276A1

公开(公告)日：2009-11-12

申请号：US12436976

申请日：2009-05-07

Applicant: Tadafumi Yoshida ,  Hiroshi Osada ,  Yuji Yagi

Inventor： Tadafumi Yoshida ,  Hiroshi Osada ,  Yuji Yagi

IPC: H05K7/06

CPC classification number: H01L23/367 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/0061 ,  H05K3/341 ,  H05K2201/09054 ,  H05K2201/09745 ,  H01L2924/00

Abstract: There is provided an electronic component which comprises an insulating member on which an electronic element is mounted, and a thermal diffusion member on which the insulating member is mounted, wherein a thermal expansion coefficient of the insulating member is lower than a thermal expansion coefficient of the thermal diffusion member, and the insulating member is mounted in an embedded manner in a recess formed on a surface of the thermal diffusion member.

Abstract translation: 提供了一种电子部件，其包括安装电子元件的绝缘部件和安装有绝缘部件的热扩散部件，其中绝缘部件的热膨胀系数低于绝缘部件的热膨胀系数 热扩散构件和绝缘构件以嵌入的方式安装在形成在热扩散构件的表面上的凹部中。

公开(公告)号：US07616171B2

公开(公告)日：2009-11-10

申请号：US11857660

申请日：2007-09-19

Applicant: Taiga Matsushita ,  Katumi Katakura ,  Katsuyoshi Matsuura

Inventor： Taiga Matsushita ,  Katumi Katakura ,  Katsuyoshi Matsuura

IPC: H01Q1/36

CPC classification number: H05K3/4685 ,  G06K19/07749 ,  G06K19/0775 ,  H05K3/4664 ,  H05K2201/09745

Abstract: The present invention discloses a connecting part of conductor pattern, which is connected to a conductor pattern formed on a surface of an insulating substrate and which has at least one dent on the surface, and a conductor patterns-connected structure obtained by electrically connecting the connecting parts of conductor patterns, mentioned above, to each other with a conductive material which fills the inside of the dent of each connecting part and further is adhered to each connecting part.

Abstract translation: 本发明公开了一种导体图案的连接部，其与形成在绝缘基板的表面上的导体图案连接，并且在表面具有至少一个凹痕，并且通过将连接 如上所述的导体图案的一部分彼此具有填充每个连接部分的凹部内部的导电材料，并且还粘附到每个连接部分。

公开(公告)号：US07611040B2

公开(公告)日：2009-11-03

申请号：US11579505

申请日：2006-04-25

Applicant: Takashi Kitae ,  Seiichi Nakatani ,  Toshiyuki Kojima ,  Shingo Komatsu ,  Yoshihisa Yamashita

Inventor： Takashi Kitae ,  Seiichi Nakatani ,  Toshiyuki Kojima ,  Shingo Komatsu ,  Yoshihisa Yamashita

IPC: B23K31/02 ,  H01L21/44

CPC classification number: H05K3/3484 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/1152 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/323 ,  H05K3/3436 ,  H05K2201/09745 ,  H05K2201/10977 ,  H05K2203/0108 ,  H05K2203/0113 ,  H05K2203/043 ,  H05K2203/0465 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/29099

Abstract: A method for forming solder bumps for realizing high density mounting and a highly reliable method for mounting a semiconductor device is provided. A flat plate having a plurality of projections or recesses thereon is prepared; the flat plate is aligned to oppose an electronic component and a resin composition including a solder powder is supplied to a gap between the flat plate and the electronic component; the resin composition is annealed to melt the solder powder included in the resin composition for growing the solder powder up to the level of the surface of the flat plate by allowing the melted solder powder to self-assemble on terminals, so as to form solder bumps on the terminals; and the flat plate is removed after cooling and solidifying the solder bumps. Thus, the solder bumps having pits corresponding to the projections or having protrusions corresponding to the recesses are formed.

Abstract translation: 提供一种用于形成用于实现高密度安装的焊料凸块的方法和用于安装半导体器件的高可靠性方法。 制备其上具有多个突起或凹部的平板; 将平板对准电子部件，将包含焊料粉末的树脂组合物供给到平板和电子部件之间的间隙; 对树脂组合物进行退火，通过使熔融的焊料粉末在端子上自组装，将包含在树脂组合物中的焊料粉末熔化成使焊料粉末生长直至平板表面的水平，从而形成焊料凸块 在终端上 并且在冷却并固化焊料凸块之后去除平板。 因此，形成具有对应于突起或具有与凹部对应的突起的凹坑的焊料凸块。

公开(公告)号：US20090223707A1

公开(公告)日：2009-09-10

申请号：US12041916

申请日：2008-03-04

Applicant: Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

Inventor： Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

IPC: H05K1/02 ,  H05K3/20

CPC classification number: H05K1/0224 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09054 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147

Abstract: Magnetic field distribution and mutual capacitance control for transmission lines are provided. A first circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, and attaching a first trace to the second surface of the dielectric material. A surface profile of the reference plane layer is modified to decrease a resistance of a return current signal path through the reference plane layer, to reduce a magnetic field coupling between the first trace and a second trace. A second circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, attaching a trace to the dielectric material, and forming a solder mask layer on the dielectric material layer over the trace. An effective dielectric constant of the solder mask layer is modified to reduce or increase a mutual capacitance between the first trace and a second trace on the dielectric material.

Abstract translation: 提供传输线的磁场分布和互电容控制。 通过将参考平面层附着到介电材料层并且将第一迹线附接到电介质材料的第二表面来制造第一电路板。 修改参考平面层的表面轮廓以减小通过参考平面层的返回电流信号路径的电阻，以减小第一迹线和第二迹线之间的磁场耦合。 通过将参考平面层附着到电介质材料层，将迹线附着到电介质材料上，以及在迹线上的介电材料层上形成焊料掩模层来制造第二电路板。 修改焊接掩模层的有效介电常数以减小或增加介电材料上的第一迹线和第二迹线之间的互电容。

公开(公告)号：US20090190320A1

公开(公告)日：2009-07-30

申请号：US12362354

申请日：2009-01-29

Applicant: ICHIO SHIMIZU ,  Kenya Kawano ,  Kisho Ashida ,  Yuichi Machida

Inventor： ICHIO SHIMIZU ,  Kenya Kawano ,  Kisho Ashida ,  Yuichi Machida

IPC: H05K7/04 ,  H01L23/48

CPC classification number: H05K7/04 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/28 ,  H01L24/29 ,  H01L24/36 ,  H01L24/39 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K3/202 ,  H05K3/321 ,  H05K3/3442 ,  H05K2201/0397 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09745 ,  H05K2201/1003 ,  H05K2201/10484 ,  H05K2201/10636 ,  H05K2201/10924 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Coupling reliability of a passive component is improved to increase the reliability of a semiconductor device. A first through hole is formed in a first electrode part of a first plate-like lead, and a second through hole is formed in a second electrode part of a second plate-like lead. As a result, at the first electrode part of the first plate-like lead, one external terminal of the passive component can be coupled to the first electrode parts on both sides of the first through hole while being laid across the first through hole. Also, at the second electrode part of the second plate-like lead, the other external terminal of the passive component can be coupled to the second electrode parts on both sides of the second through hole while being laid across the second through hole. Accordingly, at central portions both in the longitudinal and width directions of the passive component, the passive component is surrounded by sealing members. As a result, thermal stress applied to jointing materials such as solder can be reduced, improving the reliability of the semiconductor device (semiconductor package).

Abstract translation: 改善了无源部件的耦合可靠性，以提高半导体器件的可靠性。 第一通孔形成在第一板状引线的第一电极部分中，第二通孔形成在第二板状引线的第二电极部分中。 结果，在第一板状引线的第一电极部分，无源部件的一个外部端子可以被连接到第一通孔的两侧的第一电极部分，同时跨过第一通孔。 此外，在第二板状引线的第二电极部分，无源部件的另一个外部端子可以在跨过第二通孔而被布置在第二通孔的两侧上的第二电极部件上。 因此，在无源部件的纵向和宽度方向的中心部分处，被动部件被密封部件包围。 结果，可以减少施加到诸如焊料的接合材料的热应力，从而提高半导体器件（半导体封装）的可靠性。

公开(公告)号：US20090115036A1

公开(公告)日：2009-05-07

申请号：US11939622

申请日：2007-11-14

Applicant: Seung-Woo SHIN

Inventor： Seung-Woo SHIN

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/58 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/108 ,  H05K3/243 ,  H05K2201/09745 ,  H05K2203/0369 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor chip package having a metal bump and related method of fabrication are provided. The semiconductor chip package includes first and second bonding pads separated on a substrate, an insulating layer from on the substrate with first and second openings respectively exposing the first and second bonding pads, and an oxidation preventing pattern formed from a nickel layer and a silver layer and formed on the first and second bonding pads.

Abstract translation: 提供了具有金属凸块的半导体芯片封装和相关的制造方法。 半导体芯片封装包括在基板上分离的第一和第二焊盘，来自基板的绝缘层，第一和第二开口分别露出第一和第二焊盘，以及由镍层和银层形成的防氧化图案 并形成在第一和第二接合焊盘上。

公开(公告)号：US20090081861A1

公开(公告)日：2009-03-26

申请号：US11873616

申请日：2007-10-17

Applicant: Shih-Ping HSU

Inventor： Shih-Ping HSU

IPC: H01L21/44

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K3/064 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2203/0369 ,  Y02P70/611 ,  H01L2224/05599

Abstract: A manufacturing method of a solder ball disposing surface structure on a core board including: providing a core board with a first metal layer and an opposing metal bump-equipped second metal layer; forming resists on the first and second metal layers respectively; forming third, fourth and fifth openings in the resists; removing the first and second metal layers in the third and fourth openings to form first and second circuit layers and metal pads respectively; removing the metal bumps in the fifth openings to form metal flanges; removing the resists; forming first and second insulative protection layers on the first and second circuit layers and metal pads respectively; forming first and second openings in the first and second insulative protection layers to expose the first circuit layer as electrical connecting pads and expose the metal flanges respectively. Accordingly, increased contact surface area for mounting conductive elements prevents detachment thereof.

Abstract translation: 1.一种芯板上的焊球配置面结构的制造方法，其特征在于，包括：为芯板提供第一金属层和相对的金属凸块配置的第二金属层; 分别在第一和第二金属层上形成抗蚀剂; 在抗蚀剂中形成第三，第四和第五开口; 去除第三和第四开口中的第一和第二金属层，以分别形成第一和第二电路层和金属焊盘; 去除第五开口中的金属凸块以形成金属凸缘; 去除抗蚀剂; 在第一和第二电路层和金属焊盘上分别形成第一和第二绝缘保护层; 在所述第一绝缘保护层和所述第二绝缘保护层中形成第一和第二开口以将所述第一电路层暴露为电连接焊盘并分别暴露所述金属凸缘。 因此，用于安装导电元件的增加的接触表面积防止其分离。

公开(公告)号：US07501839B2

公开(公告)日：2009-03-10

申请号：US11607973

申请日：2006-12-04

Applicant: Benson Chan ,  Frank D. Egitto ,  Voya R. Markovich

Inventor： Benson Chan ,  Frank D. Egitto ,  Voya R. Markovich

IPC: G01R31/02

CPC classification number: G01R1/06711 ,  G01R1/0735 ,  G01R1/07378 ,  H05K1/0393 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09627 ,  H05K2201/09745 ,  H05K2201/10378

Abstract: A test apparatus which uses a pair of substrates and housing to interconnect a host substrate (e.g., PCB) to an electronic device (e.g., semiconductor chip) to accomplish testing of the device. The apparatus includes a housing designed for being positioned on the PCB and have one of the substrates oriented therein during device engagement. The engaging contacts of the upper (second) substrate are sculpted to assure effective chip connection.

Abstract translation: 一种测试装置，其使用一对基板和壳体将主机基板（例如，PCB）与电子设备（例如，半导体芯片）相互连接，以实现设备的测试。 该装置包括被设计用于定位在PCB上的壳体，并且在装置接合期间其中一个基板定向于其中。 上（第二）衬底的接合触点被雕刻以确保有效的芯片连接。