公开(公告)号：US20130082374A1

公开(公告)日：2013-04-04

申请号：US13439228

申请日：2012-04-04

申请人： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

发明人： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC分类号： H01L23/498

CPC分类号： H01L25/0657 ,  G11C5/063 ,  H01L23/12 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/1715 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

摘要： A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

摘要翻译： 微电子组件可以包括在其相应的第一和第二表面处具有第一和第二面板触点的电路板，以及每个具有安装到各个面板触点的端子的第一和第二微电子封装。 每个封装可以包括具有面和其上的触点的微电子元件，具有第一和第二表面的基板，以及在第二表面上的端子，用于将封装与外部元件连接。 端子可以包括在第一和第二平行网格内的位置处的第一端子。 第一终端可以被配置为承载可用于封装内的电路的地址信息，以从微电子元件内的存储器存储阵列的所有可寻址的存储器单元中确定可寻址的存储器位置。 第一网格中的第一终端的信号分配可以是第二网格中的第一终端的信号分配的镜像。

公开(公告)号：US08410618B2

公开(公告)日：2013-04-02

申请号：US13196192

申请日：2011-08-02

申请人： Belgacem Haba ,  Philip Damberg ,  Philip R. Osborn

发明人： Belgacem Haba ,  Philip Damberg ,  Philip R. Osborn

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49816 ,  H01L21/50 ,  H01L23/13 ,  H01L23/49861 ,  H01L24/01 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/91 ,  H01L2224/05554 ,  H01L2224/40091 ,  H01L2224/40225 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/4813 ,  H01L2224/4824 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/48477 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/49112 ,  H01L2224/4942 ,  H01L2224/49427 ,  H01L2224/49429 ,  H01L2224/4945 ,  H01L2224/85051 ,  H01L2224/85191 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19107 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/48095 ,  H01L2224/37099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact.

摘要翻译： 微电子组件包括半导体芯片，其具有在第一面处露出的芯片触点和与芯片的表面并置的衬底。 导电接合元件可以将第一芯片触点与衬底的第一衬底接触电连接，并且第二导电结合元件可以将第一芯片触点与第二衬底触点电连接。 第一结合元件可以具有冶金地连接到第一芯片触点的第一端和冶金地连接到第一衬底触点的第二端。 第二结合元件的第一端可以冶金地连接到第一结合元件。 第二结合元件可以或可以不接触第一芯片触点或基板触点。 第三接合元件可以连接到第一和第二接合元件的端部，所述第一和第二接合元件连接到衬底触点或芯片触点。 在一个实施例中，接合元件可以具有环形连接，其具有在第一接触处连接的第一端和第二端以及与第二接触接合的中间部。

公开(公告)号：US08378487B2

公开(公告)日：2013-02-19

申请号：US13356752

申请日：2012-01-24

申请人： Teck-Gyu Kang ,  Belgacem Haba ,  Guilian Gao

发明人： Teck-Gyu Kang ,  Belgacem Haba ,  Guilian Gao

IPC分类号： H01L21/44

CPC分类号： H01L24/16 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L24/81 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2224/29099

摘要： Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.

摘要翻译： 公开了包括具有倾斜侧壁的立管和制造这种芯片封装的方法的晶片级芯片封装。 本发明的晶片级芯片封装可有利地用于各种微电子组件中。

公开(公告)号：US20130010441A1

公开(公告)日：2013-01-10

申请号：US13618514

申请日：2012-09-14

申请人： Vage Oganesian ,  Belgacem Haba ,  Craig Mitchell ,  Ilyas Mohammed ,  Piyush Savalia

发明人： Vage Oganesian ,  Belgacem Haba ,  Craig Mitchell ,  Ilyas Mohammed ,  Piyush Savalia

IPC分类号： H05K1/18 ,  H05K5/00

CPC分类号： H01L21/76819 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/97 ,  H01L25/105 ,  H01L25/117 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24227 ,  H01L2224/24247 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15165 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161 ,  Y10T29/49002 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

摘要： A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.

公开(公告)号：US20120313242A1

公开(公告)日：2012-12-13

申请号：US13155845

申请日：2011-06-08

申请人： Kazuo Sakuma ,  Philip Damberg ,  Belgacem Haba

发明人： Kazuo Sakuma ,  Philip Damberg ,  Belgacem Haba

IPC分类号： H01L23/48 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/4853 ,  H01L23/3142 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/01 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0284 ,  H05K1/0306 ,  H05K1/09 ,  H05K3/002 ,  H05K2201/0166 ,  H01L2924/00

摘要： An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.

摘要翻译： 互连衬底包括限定第一和第二横向方向的至少一个布线层的多个导电元件。 导电突起，用于粘合到基板外部的至少一个部件的导电触点，从导电元件延伸到至少一个布线层之上。 导电突起具有远离导电元件的端部和导电元件与端部之间的颈部。 端部具有在至少一个横向方向上从颈部部分向外延伸的下表面。 衬底还包括覆盖导电元件并且沿着颈部部分至少向下表面向上延伸的电介质层。 导电突起之间的电介质层的至少部分凹陷在下表面的高度之下。

公开(公告)号：US20120313238A1

公开(公告)日：2012-12-13

申请号：US13155552

申请日：2011-06-08

申请人： Hiroaki Sato ,  Yukio Hashimoto ,  Yoshikuni Nakadaira ,  Norihito Masuda ,  Belgacem Haba ,  Ilyas Mohammed ,  Philip Damberg

发明人： Hiroaki Sato ,  Yukio Hashimoto ,  Yoshikuni Nakadaira ,  Norihito Masuda ,  Belgacem Haba ,  Ilyas Mohammed ,  Philip Damberg

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L21/561 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

摘要： A microelectronic assembly may include a substrate containing a dielectric element having first and second opposed surfaces. The dielectric element may include a first dielectric layer adjacent the first surface, and a second dielectric layer disposed between the first dielectric layer and the second surface. A Young's modulus of the first dielectric layer may be at least 50% greater than the Young's modulus of the second dielectric layer, which is less than two gigapascal (GPa). A conductive structure may extend through the first and second dielectric layers and electrically connect substrate contacts at the first surface with terminals at the second surface. The substrate contacts may be joined with contacts of a microelectronic element through conductive masses, and a rigid underfill may be between the microelectronic element and the first surface. The terminals may be usable to bond the microelectronic assembly to contacts of a component external to the microelectronic assembly.

摘要翻译： 微电子组件可以包括含有具有第一和第二相对表面的电介质元件的衬底。 电介质元件可以包括与第一表面相邻的第一电介质层，以及设置在第一介电层和第二表面之间的第二电介质层。 第一电介质层的杨氏模量可以比第二电介质层的杨氏模量大至少50％，小于二千兆帕（GPa）。 导电结构可以延伸穿过第一和第二电介质层，并且将第一表面处的基板触点与第二表面上的端子电连接。 衬底触点可以通过导电块与微电子元件的触点接合，并且刚性底部填充可以在微电子元件和第一表面之间。 端子可以用于将微电子组件接合到微电子组件外部的部件的触点。

公开(公告)号：US20120273933A1

公开(公告)日：2012-11-01

申请号：US13097943

申请日：2011-04-29

申请人： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Piyush Savalia ,  Craig Mitchell

发明人： Vage Oganesian ,  Belgacem Haba ,  Ilyas Mohammed ,  Piyush Savalia ,  Craig Mitchell

IPC分类号： H01L23/12 ,  H01L21/58 ,  H01L23/488

CPC分类号： H01L25/50 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/06524 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/00

摘要： A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having a minimum thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.

摘要翻译： 微电子组件可以包括例如电介质或半导体材料的第一，第二和第三堆叠的基本平坦的元件，并且其可以具有小于10ppm /℃的CTE。组件可以是微电子封装，并且可以并入有源半导体 在第一，第二或第三元件中的一个，两个或更多个元件中的装置可以协同地作为系统级封装。 在一个示例中，具有最小厚度小于10微米的导电元件可以通过电镀形成，并且可以电连接第一，第二或第三元件中的两个或更多个。 导电元件可以完全位于另一个基本上平面的元件的表面之下。

公开(公告)号：US20120267751A1

公开(公告)日：2012-10-25

申请号：US13091800

申请日：2011-04-21

申请人： Belgacem Haba ,  Ilyas Mohammed

发明人： Belgacem Haba ,  Ilyas Mohammed

IPC分类号： H01L23/482 ,  H01L27/02 ,  H01L21/28

CPC分类号： H01L21/486 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K3/4046 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2201/10674

摘要： A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.

摘要翻译： 公开了一种用于制造互连部件的方法，包括形成远离参考表面延伸的多个金属柱。 每个柱形成具有一对相对的端面和在它们之间延伸的边缘表面。 形成接触边缘表面和相邻柱之间的填充空间的电介质层。 电介质层具有邻近第一和第二端面的第一和第二相对表面。 电介质层的热膨胀系数小于8ppm /℃。互连部件完成，使得它们在横向方向上延伸的柱的第一和第二端面之间没有互连。 第一和第二多个可湿接触部分邻近第一和第二相对表面。 可湿接触可用于将互连部件连接到微电子元件或电路板。

公开(公告)号：US08278764B1

公开(公告)日：2012-10-02

申请号：US13354772

申请日：2012-01-20

申请人： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

发明人： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L25/105 ,  H01L23/13 ,  H01L23/3128 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

摘要： A microelectronic package can include a substrate having first, second, and third apertures extending between first and second surfaces thereof, first, second, and third microelectronic elements each having a surface facing the first surface, and a plurality of terminals exposed at a central region of the second surface. The apertures can have first, second, and third axes extending in directions of the lengths of the respective apertures. The first and second axes can be parallel to one another. The third axis can be transverse to the first axis. The central region of the second surface of the substrate can be disposed between the first and second axes. The terminals can be configured to carry sufficient address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within at least one of the microelectronic elements.

摘要翻译： 微电子封装可以包括具有在其第一和第二表面之间延伸的第一，第二和第三孔的衬底，每个具有面向第一表面的表面的第一，第二和第三微电子元件，以及暴露在中心区域处的多个端子 的第二个表面。 孔可以具有在相应孔的长度方向上延伸的第一，第二和第三轴。 第一和第二轴线可以彼此平行。 第三轴线可以横向于第一轴线。 基板的第二表面的中心区域可以设置在第一和第二轴线之间。 终端可被配置为承载可用于封装内的电路的足够的地址信息，以从至少一个微电子元件内的存储器存储阵列的所有可寻址的存储单元中确定可寻址的存储器位置。

公开(公告)号：US08241959B2

公开(公告)日：2012-08-14

申请号：US12829709

申请日：2010-07-02

申请人： Belgacem Haba ,  Giles Humpston

发明人： Belgacem Haba ,  Giles Humpston

IPC分类号： H01L21/00

CPC分类号： H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/11 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399

摘要： A method of making microelectronic packages includes making a subassembly by providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, attaching a compliant layer to the top surface of the plate, the compliant layer having openings that are aligned with the openings extending through the plate, and providing electrically conductive features on the compliant layer. After making the subassembly, the bottom surface of the plate is attached with the top surface of a semiconductor wafer so that the openings extending through the plate are aligned with contacts on the wafer. At least some of the electrically conductive features on the compliant layer are electrically interconnected with the contacts on the semiconductor wafer.

摘要翻译： 制造微电子封装的方法包括通过提供具有顶表面，底表面和在顶表面和底表面之间延伸的开口的板来制造子组件，将柔性层附接到板的顶表面，顺应层具有开口， 与延伸穿过板的开口对齐，并且在柔性层上提供导电特征。 在制造子组件之后，板的底表面与半导体晶片的顶表面相连，使得延伸穿过该板的开口与晶片上的触点对准。 柔性层上的至少一些导电特征与半导体晶片上的触点电互连。