公开(公告)号：US08470613B2

公开(公告)日：2013-06-25

申请号：US13323168

申请日：2011-12-12

Applicant: Vincent R. von Kaenel

Inventor： Vincent R. von Kaenel

IPC: H01L21/00

CPC classification number: H01L25/105 ,  H01L22/32 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/05 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13144 ,  H01L2224/1319 ,  H01L2224/16225 ,  H01L2224/24225 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/82101 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one embodiment, a packaging solution for an application integrated circuit (IC) and one or more other ICs is provided. The packaging solution may support both chip-on-chip packaging of the application IC (in flip-chip connection to a package substrate) and other ICs (in non-flip chip orientation), and package-on-package packaging of the application IC and the other ICs. The package substrate may include a first set of pads proximate to the application IC to support chip-on-chip connection to the other ICs. The pads may be connected to conductors that extend underneath the application IC, to connect to the application IC. A second set of pads may be connected to package pins for package-on-package solutions. If the chip-on-chip solution proves reliable, support for the package-on-package solution may be eliminated and the package substrate may be reduced in size.

Abstract translation: 在一个实施例中，提供了一种用于应用集成电路（IC）和一个或多个其它IC的封装解决方案。 封装解决方案可以支持应用IC的片上芯片封装（与封装基板的倒装芯片连接）和其他IC（非倒装芯片方向）以及应用IC封装封装封装 和其他IC。 封装衬底可以包括靠近应用IC的第一组焊盘，以支持与其它IC的片上芯片连接。 焊盘可以连接到延伸在应用IC下面的导体，以连接到应用IC。 第二组焊盘可以连接到封装封装解决方案的封装引脚。 如果片上芯片解决方案证明是可靠的，则可以消除对封装封装解决方案的支持，并且可以减小封装衬底的尺寸。

公开(公告)号：US20130099359A1

公开(公告)日：2013-04-25

申请号：US13565396

申请日：2012-08-02

Applicant: Sung Min KIM

Inventor： Sung Min KIM

IPC: H01L23/488 ,  H01L25/07

CPC classification number: H01L25/0657 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/1161 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/11912 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/13186 ,  H01L2224/1319 ,  H01L2224/13566 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/13647 ,  H01L2224/14181 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16147 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/114 ,  H01L2224/1182

Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape.

Abstract translation: 半导体封装包括具有多个接合焊盘的半导体芯片，以半导体芯片形成的电介质构件，以暴露各个焊盘的部分并具有梯形截面形状，并且形成为覆盖露出部分的凸块 各个接合焊盘和电介质部件的一部分，并具有阶梯状截面形状。

公开(公告)号：US08378486B2

公开(公告)日：2013-02-19

申请号：US12923885

申请日：2010-10-13

Applicant: Fumihiro Bekku

Inventor： Fumihiro Bekku

IPC: H01L23/48

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/11515 ,  H01L2224/11618 ,  H01L2224/11826 ,  H01L2224/13005 ,  H01L2224/13008 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/13191 ,  H01L2224/1329 ,  H01L2224/13291 ,  H01L2224/133 ,  H01L2224/13541 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/1411 ,  H01L2224/14151 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15788 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a protective insulating film, an opening formed in the protective insulating film, an electrode pad located within the opening, a bump formed on the protective insulating film, and an interconnect. The bump includes a bump core and a conductive film. The bump core includes an insulating resin layer and a conductive resin layer located on the insulating resin layer. The conductive film is formed on at least the upper surface of the bump core. The interconnect connects the conductive film of the bump and the electrode pad.

Abstract translation: 半导体器件包括保护绝缘膜，形成在保护绝缘膜中的开口，位于开口内的电极垫，形成在保护绝缘膜上的凸起和互连。 凸块包括凸块和导电膜。 凸块包括绝缘树脂层和位于绝缘树脂层上的导电树脂层。 至少在凸起芯的上表面上形成导电膜。 互连连接凸块的导电膜和电极垫。

公开(公告)号：US20130009286A1

公开(公告)日：2013-01-10

申请号：US13471735

申请日：2012-05-15

Applicant: Young-lyong Kim ,  Jong-ho Lee ,  Moon-gi Cho ,  Hwan-sik Lim ,  Sun-hee Park

Inventor： Young-lyong Kim ,  Jong-ho Lee ,  Moon-gi Cho ,  Hwan-sik Lim ,  Sun-hee Park

IPC: H01L23/58

CPC classification number: H01L24/11 ,  H01L23/3128 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/02123 ,  H01L2224/0331 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/0519 ,  H01L2224/05191 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/0556 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05666 ,  H01L2224/0569 ,  H01L2224/05691 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/1319 ,  H01L2224/13191 ,  H01L2224/14131 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/1435 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

Abstract translation: 半导体芯片包括减轻压力以减轻印刷电路板（PCB）和半导体芯片之间的热膨胀系数（CTE）的差异以及包括半导体芯片的倒装芯片封装的影响。 半导体芯片包括耦合凸块的应力消除缓冲器和半导体芯片焊盘。

公开(公告)号：US20120306071A1

公开(公告)日：2012-12-06

申请号：US13154061

申请日：2011-06-06

Applicant: Vijay Ullal ,  Arkadii V. Samoilov

Inventor： Vijay Ullal ,  Arkadii V. Samoilov

IPC: H01L23/48 ,  H01L21/283

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10125 ,  H01L2224/10145 ,  H01L2224/11005 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Wafer-level package semiconductor devices are described that have a smallest distance between two adjacent attachment bumps smaller than about twenty-five percent (25%) of a pitch between the two adjacent attachment bumps. The smallest distance between the two adjacent attachment bumps allows for an increase in the number of attachment bumps per area without reducing the size of the bumps, which increases solder reliability. The increased solder reliability may reduce stress to the attachment bumps, particularly stress caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on.

Abstract translation: 描述了晶片级封装半导体器件，其在两个相邻附件凸起之间具有小于两个相邻附接凸起之间的间距的约百分之二十五（25％）之间的最小距离。 两个相邻的附接凸起之间的最小距离允许增加每个面积的附接凸块的数量，而不减小凸块的尺寸，这增加了焊接可靠性。 增加的焊料可靠性可以减小附着凸块的应力，特别是在热循环试验期间由CTE失配引起的应力，跌落试验期间的动态变形或循环弯曲试验等。

公开(公告)号：US08211788B2

公开(公告)日：2012-07-03

申请号：US12486771

申请日：2009-06-18

Applicant: Shyh-Ming Chang ,  Sheng-Shu Yang

Inventor： Shyh-Ming Chang ,  Sheng-Shu Yang

IPC: H01L21/44

CPC classification number: H01L21/563 ,  H01L23/295 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/13562 ,  H01L2224/136 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/29287 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/83136 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/838 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/9211 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/305 ,  H05K3/361 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/10977 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of fabricating a bonding structure having compliant bumps includes first providing a first substrate and a second substrate. The first substrate includes first bonding pads. The second substrate is disposed on one side of the first substrate and includes second bonding pads and compliant bumps disposed thereon. The second bonding pads are opposite to the first bonding pads. Next, a non-conductive adhesive layer and ball-shaped spacers are formed between the first and the second substrates. Finally, the first substrate, the non-conductive adhesive layer, and the second substrate are compressed, such that the compliant bumps on the second bonding pads of the second substrate pass through the non-conductive adhesive layer and are electrically connected to the first bonding pads of the first substrate, respectively. The ball-shaped spacers are distributed in the non-conductive adhesive layer sandwiched between the first and the second substrates for maintaining the gap therebetween.

Abstract translation: 制造具有柔顺凸块的接合结构的方法包括首先提供第一基板和第二基板。 第一衬底包括第一接合焊盘。 第二基板设置在第一基板的一侧，并且包括设置在其上的第二接合焊盘和顺应凸块。 第二接合焊盘与第一接合焊盘相对。 接下来，在第一和第二基板之间形成非导电粘合剂层和球形间隔物。 最后，第一基板，非导电粘合剂层和第二基板被压缩，使得第二基板的第二接合焊盘上的顺从凸块穿过非导电粘合剂层，并且电连接到第一接合 第一基板的焊盘。 球形间隔件分布在夹在第一和第二基板之间的非导电粘合剂层中，以保持它们之间的间隙。

公开(公告)号：US20120049079A1

公开(公告)日：2012-03-01

申请号：US12873107

申请日：2010-08-31

Applicant: Brian David Yanoff ,  Charles Gerard Woychik ,  Yanfeng Du ,  James Wilson Rose

Inventor： Brian David Yanoff ,  Charles Gerard Woychik ,  Yanfeng Du ,  James Wilson Rose

IPC: G01T1/24

CPC classification number: G01T1/244 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic assembly is provided. The assembly comprises a substrate having a plurality of conductive contacts disposed on a surface of the substrate. The substrate comprises a dielectric material. The assembly comprises a detector having a plurality of conductive contacts disposed on a surface of the detector which is adjacent to the surface of the substrate. At least one compliant interconnect is disposed between the substrate and the detector. The conductive contacts of the substrate and the conductive contacts of the detector are in electrical communication with the compliant interconnect via a conductive epoxy. The compliant interconnect comprises a polymer core having an electrically conductive outer surface. In certain embodiments, the assembly comprises an interposer. In certain embodiments, an under-fill is disposed between the surface of the substrate and the surface of the detector.

Abstract translation: 提供电子组件。 组件包括具有设置在基板的表面上的多个导电触点的基板。 基板包括电介质材料。 组件包括检测器，其具有设置在检测器的与衬底表面相邻的表面上的多个导电触点。 在衬底和检测器之间设置至少一个兼容互连。 衬底的导电触点和检测器的导电触点经由导电环氧树脂与柔性互连电连接。 兼容互连包括具有导电外表面的聚合物芯。 在某些实施例中，组件包括插入件。 在某些实施例中，底部填充物设置在基板的表面和检测器的表面之间。

公开(公告)号：US08097956B2

公开(公告)日：2012-01-17

申请号：US12402633

申请日：2009-03-12

Applicant: Vincent R. von Kaenel

Inventor： Vincent R. von Kaenel

IPC: H01L23/52

CPC classification number: H01L25/105 ,  H01L22/32 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/05 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13144 ,  H01L2224/1319 ,  H01L2224/16225 ,  H01L2224/24225 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/82101 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one embodiment, a packaging solution for an application integrated circuit (IC) and one or more other ICs is provided. The packaging solution may support both chip-on-chip packaging of the application IC (in flip-chip connection to a package substrate) and other ICs (in non-flip chip orientation), and package-on-package packaging of the application IC and the other ICs. The package substrate may include a first set of pads proximate to the application IC to support chip-on-chip connection to the other ICs. The pads may be connected to conductors that extend underneath the application IC, to connect to the application IC. A second set of pads may be connected to package pins for package-on-package solutions. If the chip-on-chip solution proves reliable, support for the package-on-package solution may be eliminated and the package substrate may be reduced in size.

Abstract translation: 在一个实施例中，提供了一种用于应用集成电路（IC）和一个或多个其它IC的封装解决方案。 封装解决方案可以支持应用IC的片上芯片封装（与封装基板的倒装芯片连接）和其他IC（非倒装芯片方向）以及应用IC封装封装封装 和其他IC。 封装衬底可以包括靠近应用IC的第一组焊盘，以支持与其它IC的片上芯片连接。 焊盘可以连接到延伸在应用IC下面的导体，以连接到应用IC。 第二组焊盘可以连接到封装封装解决方案的封装引脚。 如果片上芯片解决方案证明是可靠的，则可以消除对封装封装解决方案的支持，并且可以减小封装衬底的尺寸。

公开(公告)号：US20110291268A1

公开(公告)日：2011-12-01

申请号：US12856794

申请日：2010-08-16

Applicant: David Wei WANG ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Yi-Chang Lee

Inventor： David Wei WANG ,  An-Hong Liu ,  Hsiang-Ming Huang ,  Yi-Chang Lee

IPC: H01L23/498

CPC classification number: H01L23/481 ,  H01L21/563 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface. Hence, the reliability of multi-chip stack package structure can be enhanced with the application of these soft metal caps.

公开(公告)号：US20110249113A1

公开(公告)日：2011-10-13

申请号：US13151083

申请日：2011-06-01

Applicant: Mitsumasa KOYANAGI

Inventor： Mitsumasa KOYANAGI

IPC: H04N7/18 ,  B32B37/00

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68313 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/75 ,  H01L2224/7598 ,  H01L2224/78743 ,  H01L2224/81097 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/81907 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2224/83907 ,  H01L2224/95001 ,  H01L2224/95145 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01031

Abstract: In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 12b of semiconductor chips 13 are temporarily adhered to corresponding temporary adhesion regions 72a of a carrier substrate 73a by way of water films 81. The carrier substrate 73a is then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portions 12 of the chips 13 on the carrier substrate 73a with corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portions 12 to the predetermined positions, the chips 13 are attached to the support substrate or the circuit layer with a desired layout.

Abstract translation: 在制造具有三维堆叠结构的集成电路器件的方法中，可以以期望的精度容易且有效地执行将许多芯片形半导体电路固定到支撑衬底或具有预定布局的电路层的步骤。 半导体芯片13的临时粘合部分12b通过水膜81临时粘附到载体基板73a的相应的临时粘合区域72a上。然后将载体基板73a压向支撑基板或所需的电路层，从而接触连接部分 载体基板73a上的芯片13的12个，在支撑基板或电路层上具有对应的预定位置。 此后，通过将连接部分12固定到预定位置，芯片13以期望的布局附接到支撑基板或电路层。