公开(公告)号：US07504706B2

公开(公告)日：2009-03-17

申请号：US11514097

申请日：2006-08-31

Applicant: Madhavan Swaminathan ,  Ege Engin ,  Lixi Wan ,  Prathap Muthana

Inventor： Madhavan Swaminathan ,  Ege Engin ,  Lixi Wan ,  Prathap Muthana

IPC: H01L29/00

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09763 ,  Y10S257/904 ,  Y10S257/924 ,  H01L2924/00

Abstract: One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including installing in said package an array of embedded discrete ceramic capacitors, and optionally planar capacitor layers. A further embodiment provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including an array of embedded discrete ceramic capacitors with different resonance frequencies, arranged in such a way that the capacitor array's impedance vs frequency curve in the critical mid-frequency range yields impedance values at or below a targeted impedance value.

Abstract translation: 本发明的一个实施例提供了一种用于在1MHz至3GHz的中频范围内向IC提供低噪声电源封装的装置，包括在所述封装中安装嵌入式分立陶瓷电容器阵列，以及可选的平面电容层 。 另一实施例提供了一种用于在1MHz至3GHz的中频范围内向IC提供低噪声电源封装的装置，包括具有不同谐振频率的嵌入式分立陶瓷电容器阵列，其布置成使得电容器 阵列在关键中频范围内的阻抗与频率曲线产生等于或低于目标阻抗值的阻抗值。

公开(公告)号：US20090057910A1

公开(公告)日：2009-03-05

申请号：US11847985

申请日：2007-08-30

Applicant: Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

Inventor： Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

IPC: H01L29/00 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。

公开(公告)号：US20090056119A1

公开(公告)日：2009-03-05

申请号：US12005610

申请日：2007-12-28

Applicant: Shuhichi Okabe ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Myung Sam Kang ,  Jung Hyun Park ,  Ji Hong Jo ,  Jin Yong An ,  Soon Oh Jung

Inventor： Shuhichi Okabe ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Myung Sam Kang ,  Jung Hyun Park ,  Ji Hong Jo ,  Jin Yong An ,  Soon Oh Jung

IPC: H05K3/00

CPC classification number: H05K3/205 ,  H05K3/062 ,  H05K3/108 ,  H05K3/462 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0369 ,  H05K2203/061 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed is a method of fabricating a multilayer printed circuit board, which enables the formation of a micro circuit able to be realized through a semi-additive process using the CTE and rigidity of a metal carrier on a thin substrate which is difficult to convey.

Abstract translation: 公开了一种制造多层印刷电路板的方法，其能够形成能够通过使用CTE的半添加工艺和难以传送的薄基板上的金属载体的刚性来实现的微电路。

公开(公告)号：US20090053459A1

公开(公告)日：2009-02-26

申请号：US12257501

申请日：2008-10-24

Applicant: Naohiro Hirose ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

Inventor： Naohiro Hirose ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

IPC: B32B1/04

CPC classification number: H01L23/49811 ,  H01L2224/05001 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/15312 ,  H05K1/111 ,  H05K1/112 ,  H05K3/28 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/09381 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/10318 ,  Y10T428/239

Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.

公开(公告)号：US07491895B2

公开(公告)日：2009-02-17

申请号：US11140304

申请日：2005-05-26

Applicant: Ryosuke Usui ,  Takeshi Nakamura

Inventor： Ryosuke Usui ,  Takeshi Nakamura

IPC: H01L23/48

CPC classification number: H05K3/421 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/112 ,  H05K1/115 ,  H05K2201/0394 ,  H05K2201/0769 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09809 ,  H05K2203/0315 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wiring substrate is provided with an insulating resin film; and first and second conductive films provided on the back side and top side of the insulating resin film, respectively. The wiring substrate includes a via formed to fill a recess provided in the insulating resin film and electrically connecting the top side and back side of the insulating resin film. The via includes a first metal film formed to cover the side wall of the recess, an oxide film formed to cover the first meal film, and a second metal film formed on the metal oxide film.

Abstract translation: 布线基板设置有绝缘树脂膜; 以及分别设置在绝缘树脂膜的背侧和顶侧的第一和第二导电膜。 布线基板包括形成为填充设置在绝缘树脂膜中的凹部并电连接绝缘树脂膜的顶侧和背面的通孔。 通孔包括形成为覆盖凹部的侧壁的第一金属膜，形成为覆盖第一膳食膜的氧化膜和形成在金属氧化物膜上的第二金属膜。

公开(公告)号：US20090041994A1

公开(公告)日：2009-02-12

申请号：US11988289

申请日：2006-07-04

Applicant: Ulrich Ockenfuss ,  Thomas Gottwald

Inventor： Ulrich Ockenfuss ,  Thomas Gottwald

IPC: B32B3/00

CPC classification number: H05K1/185 ,  H01L2224/16227 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/15192 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/141 ,  H05K3/284 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/049 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2201/2036 ,  Y10T428/24917 ,  H01L2924/00

Abstract: The invention relates to a multilayer printed circuit board structure comprising a stack of plurality of electrically insulating and/or electroconductive layers and at least one passive or active electrical component arranged inside the stack of layers, the component extending laterally only in part of the surface extension of the stack of layers. The invention also relates to a passive or active electrical component mounted on the stack, to an associated wiring, and to a corresponding production method. According to the invention, the insert is embedded between two electrically insulating liquid resin layers or prepreg layers extending over the entire surface and covering the insert on both sides, the insert being surrounded by a resin material that is liquefied by compression or lamination of the structure. The invention structure can be used in printed circuit board technology.

Abstract translation: 本发明涉及一种多层印刷电路板结构，其包括多个电绝缘和/或导电层的堆叠以及布置在层叠层内的至少一个无源或有源电气元件，所述元件横向延伸仅部分表面延伸部分 的堆叠层。 本发明还涉及安装在堆叠上的无源或有源电气部件，相关布线以及相应的制造方法。 根据本发明，插入物嵌入两个在整个表面上延伸并且在两侧覆盖插入物的电绝缘液体树脂层或预浸料层之间，插入物由树脂材料包围，该树脂材料通过压缩或层压结构液化 。 本发明的结构可用于印刷电路板技术。

公开(公告)号：US20080313887A1

公开(公告)日：2008-12-25

申请号：US12155663

申请日：2008-06-06

Applicant: Garo Miyamoto

Inventor： Garo Miyamoto

IPC: H01C17/06 ,  H01C17/00

CPC classification number: H05K1/167 ,  H05K3/0032 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/0554 ,  H05K2203/107 ,  H05K2203/1453 ,  H05K2203/171 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: The present invention provides a method of producing a resistance element incorporated in a printed circuit board at an accuracy of resistance value of ±1% or less, at low cost and with a good yield while the resistance element formed by a resistor paste is incorporated. A method of producing a printed circuit board incorporating a resistance element includes: preparing a double-sided copper clad board having a first metallic foil on one face of an insulating base material thereof and a second metallic foil on the other face of the insulating base material thereof; providing at least a pair of electrodes on one of the metallic foils; printing a resistor paste between the electrodes to form a resistor; preparing a circuit board having at least one wiring layer; causing a layer on which the resistor paste is formed to oppose the circuit board to layer the double-sided copper clad board on the circuit board; forming openings in the first and the second metallic foils; and emitting laser through the openings to partly remove the insulating base material and the resistor paste to adjust resistance value. A conformal mask for etching may be formed on the second metallic foil to form openings in the insulating base material by etching to emit laser through the openings.

Abstract translation: 本发明提供一种以电阻值为±1％以下的精度制造电阻元件的制造方法，低成本且良好的成品率，同时结合电阻浆料形成的电阻元件。 一种制造包含电阻元件的印刷电路板的方法包括：制备在绝缘基材的一个面上具有第一金属箔的双面铜包覆板和在绝缘基材的另一面上的第二金属箔 的; 在一个金属箔上提供至少一对电极; 在电极之间印刷电阻膏以形成电阻器; 准备具有至少一个布线层的电路板; 使形成有电阻浆料的层与电路板相对地层叠电路板上的双面铜箔板; 在第一和第二金属箔中形成开口; 并通过开口发射激光以部分地去除绝缘基材和电阻浆料以调节电阻值。 可以在第二金属箔上形成用于蚀刻的保形掩模，以通过蚀刻在绝缘基材中形成开口，以通过开口发射激光。

公开(公告)号：US20080310132A1

公开(公告)日：2008-12-18

申请号：US12076118

申请日：2008-03-13

Applicant: Jun-Heyoung Park ,  Jee-Soo Mok ,  Ki-Hwan Kim ,  Sung-Yong Kim

Inventor： Jun-Heyoung Park ,  Jee-Soo Mok ,  Ki-Hwan Kim ,  Sung-Yong Kim

IPC: H05K3/02 ,  H01R9/00

CPC classification number: H05K3/4614 ,  H05K3/0035 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4647 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/061 ,  Y10T29/49156

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The method of manufacturing a printed circuit board, by forming at least one bump for interlayer conduction on a surface of a board and stacking an insulation layer on the surface of the board, can include the operations of forming at least one dam on the surface of the board that surrounds a region corresponding to the bump, forming the bump by printing conductive paste onto the region corresponding to the bump, and stacking the insulation layer onto the surface of the board. This method can be utilized to improve productivity and resolve the problem of spreading.

Abstract translation: 公开了印刷电路板和印刷电路板的制造方法。 制造印刷电路板的方法通过在基板的表面上形成至少一个用于层间导电的凸块并在该表面上堆叠绝缘层的方法可以包括在表面上形成至少一个坝的操作 围绕与凸块相对应的区域的板，通过将导电膏印刷到对应于凸块的区域上形成凸块，并将绝缘层堆叠到板的表面上。 该方法可用于提高生产力并解决传播问题。

公开(公告)号：US20080310073A1

公开(公告)日：2008-12-18

申请号：US11912559

申请日：2006-04-28

Applicant: Akihiro Kanno ,  Akiko Sugioka ,  Naohiko Abe ,  Hirotake Nakashima

Inventor： Akihiro Kanno ,  Akiko Sugioka ,  Naohiko Abe ,  Hirotake Nakashima

IPC: H01G4/018 ,  B29C71/02

CPC classification number: H05K1/162 ,  C04B35/4682 ,  C04B35/47 ,  C04B35/624 ,  C04B2235/3213 ,  C04B2235/3215 ,  C04B2235/658 ,  C04B2235/661 ,  C23C18/06 ,  C23C18/1216 ,  C23C18/1241 ,  C23C18/1254 ,  C23C18/1275 ,  C23C18/1279 ,  C23C18/1283 ,  H01G4/1209 ,  H01G4/33 ,  H01G13/00 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09509

Abstract: The present invention has an object to provide a method for forming an oxide dielectric layer, which dielectric layer is formed by applying the sol-gel method, and is hardly damaged by an etching solution and excellent in dielectric characteristics such as a large electric capacitance. To achieve the object, the forming method of an oxide dielectric layer by applying a sol-gel method characterized by being provided with the following processes (a) to (c) is employed. Process (a): A solution preparing process of preparing a sol-gel solution for manufacturing an aiming oxide dielectric layer. Process (b): A coating process wherein stages of the sol-gel solution coating on the surface of a metal substrate followed by drying in an oxygen-containing atmosphere followed by pyrolysis in an oxygen-containing atmosphere sequentially is made one unit step; the one unit step is repeated twice or more times; and a pre-baking stage at 550-deg.C to 1000-deg.C in an inert gas-substituted atmosphere or the like is provided optionally between the one unit step and the next one unit step to control the film thickness. Process (c): A baking process of finally subjecting the coated metal substrate to a baking process at 550-deg.C to 1000-deg.C in an inert gas-substituted atmosphere or the like to finish the dielectric layer.

Abstract translation: 本发明的目的是提供一种形成氧化物电介质层的方法，该电介质层通过施加溶胶 - 凝胶法形成，并且几乎不被蚀刻溶液损坏，并且具有优异的诸如大电容的介电特性。 为了达到上述目的，采用以下工序（a）〜（c）为特征的溶胶 - 凝胶法的氧化物介电层的形成方法。 方法（a）：制备用于制造瞄准氧化物介电层的溶胶 - 凝胶溶液的溶液制备方法。 方法（b）：其中在金属基材表面上涂覆溶胶 - 凝胶溶液的阶段，然后在含氧气氛中干燥，然后依次在含氧气氛中热解的步骤为一个单位步骤; 一个单位步骤重复两次或更多次; 并且在惰性气体取代气氛等中在550℃〜1000℃的预烘烤阶段可选地设置在一个单元步骤和下一个单元步骤之间，以控制膜厚度。 方法（c）：在惰性气体取代气氛等中，在550℃〜1000℃下对经涂布的金属基材进行烘烤处理的烧成工序，以完成电介质层。

公开(公告)号：US07449381B2

公开(公告)日：2008-11-11

申请号：US11352279

申请日：2006-02-13

Applicant: Rabindra N. Das ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

Inventor： Rabindra N. Das ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC: H01L21/8234 ,  H01L21/00

CPC classification number: H05K1/162 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2203/013 ,  H05K2203/0568

Abstract: A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. The capacitive substrate may be incorporated within a larger circuitized substrate, e.g., to form an electrical assembly. A method of making an information handling system including such substrates is also provided.

Abstract translation: 一种形成电容衬底的方法，其中材料的至少一个电容介电层被屏幕或喷墨印刷到导体上，然后进一步处理衬底，包括添加通孔以将所选择的元件耦合到衬底内以形成 至少两个电容器作为衬底的内部元件。 电容性衬底可以结合在更大的电路化衬底内，例如以形成电组件。 还提供了一种制造包括这种基板的信息处理系统的方法。