公开(公告)号：US09961764B2

公开(公告)日：2018-05-01

申请号：US14069402

申请日：2013-11-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiromichi Kitajima

IPC: H05K1/00 ,  H05K1/02 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18 ,  H05K7/06 ,  H05K3/46

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/181 ,  H05K3/4629 ,  H05K7/06 ,  H05K2201/09381 ,  H05K2201/0979 ,  H05K2201/099 ,  H01L2924/00

Abstract: A via conductor connected to a mounting electrode near a corner portion of a circuit substrate is provided in a position in a corresponding mounting electrode, located closer to the center of the circuit substrate. Thus, concentration of a stress in a portion of the via conductor is effectively reduced, and a break, a chip, or a crack is prevented from occurring to the circuit substrate. Even if the portion located closer to the corner portion of the mounting electrode is peeled from the circuit substrate, the electrical characteristics of the circuit module are secured because disconnection between the corresponding mounting electrode and the via conductor is prevented.

公开(公告)号：US20180116056A1

公开(公告)日：2018-04-26

申请号：US15849624

申请日：2017-12-20

Applicant: Unimicron Technology Corp.

Inventor： Yin-Ju CHEN ,  Ming-Hao WU ,  Cheng-Po YU

IPC: H05K3/46 ,  H05K1/18 ,  H01L23/12 ,  H01L23/498 ,  H01L35/30 ,  H05K1/02 ,  H05K3/36 ,  G06F1/20 ,  H05K1/14 ,  H05K1/11

CPC classification number: H05K3/4647 ,  G06F1/206 ,  H01L23/12 ,  H01L23/13 ,  H01L23/4275 ,  H01L23/49827 ,  H01L35/30 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15153 ,  H01L2924/15313 ,  H05K1/0203 ,  H05K1/0206 ,  H05K1/113 ,  H05K1/14 ,  H05K1/181 ,  H05K1/185 ,  H05K1/187 ,  H05K3/36 ,  H05K3/4697 ,  H05K2201/048 ,  H05K2201/10219 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734

Abstract: A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.

公开(公告)号：US20180098420A1

公开(公告)日：2018-04-05

申请号：US15549107

申请日：2015-08-20

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI ,  Wataru SHIROI ,  Kenichi KUBOYAMA

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K3/40

CPC classification number: H05K1/0248 ,  H01L23/32 ,  H01L25/04 ,  H01L25/18 ,  H01L2224/16225 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/113 ,  H05K1/119 ,  H05K1/141 ,  H05K1/16 ,  H05K1/18 ,  H05K1/181 ,  H05K1/182 ,  H05K3/4046 ,  H05K7/02 ,  H05K2201/09218 ,  H05K2201/10378

Abstract: A semiconductor device according to an embodiment has a first semiconductor component and a second semiconductor component which are electrically connected with each other via an interposer. The interposer has a plurality of first signal wiring paths, and a plurality of second signal wiring paths each having a path distance smaller than each of the plurality of first signal wiring paths. Furthermore, the first semiconductor component includes a first electrode, a second electrode, and a third electrode arranged in order in a first direction. Furthermore, the second semiconductor component includes a fourth electrode, a fifth electrode, and a sixth electrode arranged in order in the first direction. Furthermore, the first electrode is connected with the fourth electrode via the first signal wiring path, the second electrode is connected with the fifth electrode via the first signal wiring path, and the third electrode is connected with the sixth electrode via the first signal wiring path.

公开(公告)号：US20180092219A1

公开(公告)日：2018-03-29

申请号：US15361075

申请日：2016-11-25

Applicant: Unimicron Technology Corp.

Inventor： Cheng-Chieh CHIU ,  Chia-Chan CHANG ,  Chun-Yi KUO ,  Yu-Cheng LIN

IPC: H05K3/06 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/061 ,  H05K1/113 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/096 ,  H05K2203/0502

Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

公开(公告)号：US20180092213A1

公开(公告)日：2018-03-29

申请号：US15710579

申请日：2017-09-20

Applicant: Apple Inc.

Inventor： Corey S. Provencher ,  Meng Chi Lee ,  Derek J. Walters ,  Ian A. Spraggs ,  Flynn P. Carson ,  Shakti S. Chauhan ,  Daniel W. Jarvis ,  David A. Pakula ,  Jun Zhai ,  Michael V. Yeh ,  Alex J. Crumlin ,  Dennis R. Pyper ,  Amir Salehi ,  Vu T. Vo ,  Gregory N. Stephens

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34

CPC classification number: H05K1/181 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/115 ,  H05K1/144 ,  H05K3/0014 ,  H05K3/284 ,  H05K3/341 ,  H05K3/3436 ,  H05K2201/10159 ,  H05K2201/10674 ,  H05K2203/1316 ,  Y02P70/611

Abstract: The present disclosure is related to printed circuit board packages and methods of assembly that may be used in the fabrication of electrical devices. Printed circuit board packages may be manufactured by stacking printed circuit board assemblies. Each printed circuit board assembly may have multiple printed circuit boards supported by a resin mold. The printed circuit board assemblies may be shaped to improve space utilization efficiency and to accommodate large electrical components that are attached to the printed circuit board package.

公开(公告)号：US20180007780A1

公开(公告)日：2018-01-04

申请号：US15461861

申请日：2017-03-17

Applicant: NGK INSULATORS, LTD.

Inventor： Hiroshi TAKEBAYASHI ,  Natsuki HIRATA ,  Rishun KIN

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/36 ,  H05K3/40

CPC classification number: H05K1/028 ,  H05K1/0281 ,  H05K1/113 ,  H05K1/116 ,  H05K3/363 ,  H05K3/4038 ,  H05K2201/09027 ,  H05K2201/09572 ,  H05K2201/09909

Abstract: A connection FPC 75 includes a plurality of metal wires 750 between a support layer 751 and a covering layer 752, and an exposed region including contacts 753 serving as end portions of the metal wires 750 is exposed from the covering layer 752. A bending-position guide 760 is provided on the surface of the support layer 751 opposite from the surface on which the metal wires 750 are provided. An edge 760a of the bending-position guide 760 serves as a bending line along which the connection FPC 75 is bent and is disposed in a covering-layer projection area E where the covering layer 752 is projected on the support layer 751. The connection FPC 75 is bent at portions of the metal wires 750 covered with the covering layer 752, that is, at reinforced portions.

公开(公告)号：US09859130B2

公开(公告)日：2018-01-02

申请号：US14568084

申请日：2014-12-11

Applicant: Unimicron Technology Corp.

Inventor： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

IPC: H01L21/48 ,  H05K1/11 ,  H05K3/46 ,  C25D1/00 ,  H05K3/42

CPC classification number: H01L21/481 ,  C25D1/003 ,  H05K1/113 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T156/10

Abstract: A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal cattier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads. An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.

公开(公告)号：US20170374738A1

公开(公告)日：2017-12-28

申请号：US15682049

申请日：2017-08-21

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H05K1/09 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11

CPC classification number: H05K1/097 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/113 ,  H05K1/165 ,  H05K3/188 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/5313 ,  H01L2924/00

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

公开(公告)号：US20170359896A1

公开(公告)日：2017-12-14

申请号：US15618256

申请日：2017-06-09

Applicant: Board of Regents, The University of Texas System

Inventor： Chi Yen Kim ,  Ryan Wicker ,  Eric MacDonald ,  David Espalin

IPC: H05K1/11 ,  H01R12/57 ,  H05K3/40 ,  H05K3/10

CPC classification number: H05K1/113 ,  H05K3/103 ,  H05K3/381 ,  H05K3/4015 ,  H05K3/4046 ,  H05K2201/0355 ,  H05K2201/10242 ,  H05K2201/10257 ,  H05K2201/1028 ,  H05K2201/10303 ,  H05K2203/0228 ,  H05K2203/0271 ,  H05K2203/1105 ,  H05K2203/1189 ,  H05K2203/1446

Abstract: A 3D printed circuit apparatus includes a 3D printed circuit having a surface layer and one or more wires embedded under the surface layer, and a conductive metal pin that is cut to a desired length and inserted into the 3D printed circuit in order to attain contact with the wire or wires embedded under the surface layer.

公开(公告)号：US09844135B2

公开(公告)日：2017-12-12

申请号：US14480430

申请日：2014-09-08

Applicant: Cisco Technology, Inc.

Inventor： Feng Wu ,  Yongchao Ji ,  Yang Tang ,  Stephen Scearce ,  Shunjia Liu ,  Shaochun Tang

IPC: H05K7/00 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34

CPC classification number: H05K1/115 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K1/181 ,  H05K3/3415 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/10015 ,  H05K2201/10674

Abstract: Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.