公开(公告)号：US06361923B1

公开(公告)日：2002-03-26

申请号：US09375957

申请日：1999-08-17

申请人： John S. Kresge ,  John M. Lauffer ,  David J. Russell

发明人： John S. Kresge ,  John M. Lauffer ,  David J. Russell

IPC分类号： G03C173

CPC分类号： H05K3/0032 ,  B23K2103/42 ,  B23K2103/50 ,  B41M5/24 ,  H05K1/0326 ,  H05K1/0373 ,  H05K2201/0112 ,  Y10S430/146

摘要： An epoxy based resin which exhibits good laser ablation and good adherence to a substrate such a copper is provided by adding to the resin a dye or dyes having substantial energy absorption at the emission wave lengths of lasers used to laser ablate the resin. The resin with the dye or dyes included is coated onto a substrate and cured, or laminated onto a substrate in the cured condition. The required openings are formed in the cured film by laser ablation. This allows for the use of optimum techniques to be used to form micro vias.

公开(公告)号：US06204456B1

公开(公告)日：2001-03-20

申请号：US09159938

申请日：1998-09-24

申请人： John M. Lauffer ,  Voya R. Markovich ,  Cheryl L. Palomaki ,  William E. Wilson

发明人： John M. Lauffer ,  Voya R. Markovich ,  Cheryl L. Palomaki ,  William E. Wilson

IPC分类号： H01R909

CPC分类号： H05K3/0094 ,  H01R12/523 ,  H05K3/0023 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49165

摘要： Methods of filling apertures, for example, through holes, in substrates are provided. The methods utilize a dielectric film, preferably a photoimageable dielectric film, which is employed to fill the apertures and to form a dielectric film disposed above the substrate at the same time. As a result, the aperture fill material is the same as, and indeed continuous with, the dielectric film which is disposed on the substrate. The method employs the following steps: providing a substrate having apertures; providing a dielectric film disposed on the substrate covering the apertures, reflowing the dielectric film to flow into the apertures and to form a dielectric film adherent to the substrate, to provide a continuous dielectric extending from the dielectric film into the apertures. In certain embodiments, after filling, additional apertures, such as vias, are photoimaged in the dielectric film. Preferably the vias are then metallized, and circuitry formed atop the dielectric film.

摘要翻译： 提供了在基板中填充孔的方法，例如通孔。 该方法利用电介质膜，优选可光成像的介电膜，其用于填充孔并同时形成设置在基板上方的电介质膜。 结果，孔填充材料与设置在基底上的电介质膜相同，实际上是连续的。 该方法采用以下步骤：提供具有孔的基底; 提供设置在覆盖所述孔的基板上的电介质膜，回流所述电介质膜流入所述孔中并形成与所述衬底粘附的电介质膜，以提供从所述电介质膜延伸到所述孔中的连续电介质。 在某些实施例中，在填充之后，附加的孔，例如通孔，在电介质膜中被光刻。 优选地，将通孔金属化，并且在电介质膜的顶部形成电路。

公开(公告)号：US6009619A

公开(公告)日：2000-01-04

申请号：US864632

申请日：1997-05-28

申请人： John M. Lauffer

发明人： John M. Lauffer

IPC分类号： H05K1/00 ,  H05K1/11 ,  H05K3/00 ,  H05K3/22 ,  H05K3/34 ,  H05K3/40 ,  H05K3/46 ,  H05K3/02

CPC分类号： H05K1/112 ,  H05K3/0023 ,  H05K3/225 ,  H05K3/3442 ,  H05K3/4652 ,  H05K1/0292 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/09472 ,  H05K2201/10636 ,  H05K2203/0551 ,  H05K3/3452 ,  H05K3/4038 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49149 ,  Y10T29/49156

摘要： An electronic circuit card and a process of manufacturing the electronic circuit card. The process includes the steps of providing the electronic circuit card with external electrical circuits. A photoimageable dielectric layer is formed on the electronic circuit card. A metal foil layer is laminated on the photoimageable dielectric layer and the metal foil layer is patterned to form a wire and a component add land pattern. The photoimageable dielectric layer is patterned and the wire and the component add land pattern are electrically connected to the electronic circuit card.

摘要翻译： 一种电子电路卡及其制造方法。 该过程包括为电子电路卡提供外部电路的步骤。 在电子电路卡上形成可光成像的电介质层。 在可光成像的介电层上层压金属箔层，对金属箔层进行图案化以形成导线和添加焊盘图案的部件。 将可光成像的介质层图案化，并将导线和部件添加焊盘图案电连接到电子电路卡。

公开(公告)号：US5977642A

公开(公告)日：1999-11-02

申请号：US918085

申请日：1997-08-25

申请人： Bernd K. Appelt ,  Saswati Datta ,  Michael A. Gaynes ,  John M. Lauffer ,  James R. Wilcox

发明人： Bernd K. Appelt ,  Saswati Datta ,  Michael A. Gaynes ,  John M. Lauffer ,  James R. Wilcox

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/498 ,  H05K3/32 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/81 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49811 ,  H05K3/325 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0307 ,  H05K2203/0723 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A method is provided for connecting two conductive surfaces in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive surface, applying a dielectric insulation material over the first conductive surface such that the dendrites are exposed through the insulation material to leave a substantially planar surface of exposed dendrites, and placing a second conductive surface on top of the exposed dendrites. The second conductive surface may be a surface metal, a chip bump array, or a ball grid array. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection and planarization manufactured in accordance with the present invention.

摘要翻译： 提供了一种用于连接电子电路封装中的两个导电表面的方法，包括以下步骤：在第一导电表面的选定区域上形成枝晶，在第一导电表面上施加介电绝缘材料，使得枝晶通过绝缘材料暴露于 留下暴露的树突的基本上平坦的表面，并将第二导电表面放置在暴露的树突上。 第二导电表面可以是表面金属，芯片凸块阵列或球栅阵列。 还要求保护的是包含用于根据本发明制造的电互连和平坦化的树突的电子电路封装。

公开(公告)号：US5571593A

公开(公告)日：1996-11-05

申请号：US467558

申请日：1995-06-06

申请人： Roy L. Arldt ,  Christina M. Boyko ,  Burtran J. Cayson ,  Richard M. Kozlowski ,  Joseph D. Kulesza ,  John M. Lauffer ,  Philip C. Liu ,  Voya R. Markovich ,  Issa S. Mahmoud ,  James F. Muska ,  Kostas Papathomas ,  Joseph G. Sabia ,  Richard A. Schumacher

发明人： Roy L. Arldt ,  Christina M. Boyko ,  Burtran J. Cayson ,  Richard M. Kozlowski ,  Joseph D. Kulesza ,  John M. Lauffer ,  Philip C. Liu ,  Voya R. Markovich ,  Issa S. Mahmoud ,  James F. Muska ,  Kostas Papathomas ,  Joseph G. Sabia ,  Richard A. Schumacher

IPC分类号： B32B7/04 ,  C08G59/40 ,  C08G73/00 ,  C08L63/00 ,  C09D163/00 ,  H01B1/20 ,  H01B1/22 ,  H01B1/24 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16 ,  H05K3/00 ,  H05K3/40 ,  B32B9/00

CPC分类号： H01B1/24 ,  B32B7/04 ,  H01B1/22 ,  H05K1/095 ,  H05K1/113 ,  H05K1/167 ,  H05K3/4053 ,  H05K3/4069 ,  H01L2224/16235 ,  H05K1/16 ,  H05K2201/0347 ,  H05K2201/09563 ,  H05K2201/10734 ,  H05K2203/0126 ,  H05K2203/0191 ,  H05K2203/0207 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0763 ,  H05K3/0023 ,  H05K3/0047 ,  H05K3/0094 ,  Y10S428/901 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24273 ,  Y10T428/24331 ,  Y10T428/24339 ,  Y10T428/24826 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/25

摘要： The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.

摘要翻译： 本发明允许焊接接头直接制成通孔和通孔，而不会通过用环氧树脂或氰酸盐填充组合物填充电镀通孔，焊料不会被弄脏到通孔或通孔中。 当固化和过度镀覆时，填充组合物为焊接接头提供支撑，并为相互连接提供平坦的可焊接表面。 在某些实施方案中，固化的填充组合物提供另外的导电性的优点。 本发明还涉及用这种填充组合物填充通孔的几种新方法，以及位于通孔和通孔中的电阻器。

公开(公告)号：US20110173809A1

公开(公告)日：2011-07-21

申请号：US12657394

申请日：2010-01-20

申请人： John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, JR. ,  Peter A. Moschak

发明人： John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, JR. ,  Peter A. Moschak

IPC分类号： H05K3/42 ,  H05K3/02 ,  H05K3/46

CPC分类号： H05K3/4641 ,  H05K3/064 ,  H05K3/4069 ,  H05K3/427 ,  H05K3/44 ,  H05K3/445 ,  H05K3/462 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0143 ,  H05K2203/068 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

摘要： Apparatus and method for making circuitized substrates using a continuous roll format in which a layer of conductor is fed into the apparatus, layers of photo-imageable dielectric are applied to opposite sides of the conductor layer, thru-holes are formed through the composite, and then metal layers are added over the dielectric and then patterns (e.g., circuit) are formed therein. Several operations are performed in addition to these to form the final end product, a circuitized substrate (e.g., printed circuit board), all while the conductor layer of the product is retained in a solid format, up to the final separation from the continuous layer.

摘要翻译： 使用连续辊式制造电路化基板的装置和方法，其中导体层被馈送到装置中，可光成像电介质层被施加到导体层的相对侧，穿过复合材料形成通孔， 然后在电介质上添加金属层，然后在其中形成图案（例如电路）。 除了这些之外，还进行了几个操作以形成最终终端产品，电路化基板（例如，印刷电路板），同时产品的导体层保持为固体形式，直到与连续层的最终分离 。

公开(公告)号：US07814649B2

公开(公告)日：2010-10-19

申请号：US11482945

申请日：2006-07-10

申请人： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

发明人： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

IPC分类号： H05K3/02 ,  H05K3/10

CPC分类号： H05K3/44 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/0052 ,  H05K3/429 ,  H05K3/4641 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A method of making a circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer.

摘要翻译： 一种制造电路化衬底的方法，该衬底包括沿着其至少一个导电层的侧边缘部分的多个邻接的开放段，这些开放段通过电介质材料的屏障隔开，其基本上填充开放段，例如在 层压工艺，其将基板的两个电介质层粘合到导电层。

公开(公告)号：US07800916B2

公开(公告)日：2010-09-21

申请号：US11783306

申请日：2007-04-09

申请人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

发明人： Kim J. Blackwell ,  Frank D. Egitto ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： H01R12/16

CPC分类号： H05K1/186 ,  H01L23/4985 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/4611 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/10515 ,  H05K2201/10681 ,  Y10T29/49126 ,  Y10T29/49151 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

摘要： A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.

摘要翻译： 电路化衬底组件由至少两个电路化衬底组成，每个衬底均包括薄介电层和具有多个导电构件作为其一部分的导电层，每个衬底的导电构件电耦合到半导体芯片的导电部位。 电介质层位于两个基板之间，并且基板接合在一起，使得芯片在内部位于组件内并且以堆叠取向定向。 还提供了制造这种组件的方法，以及使用其的电组件以及适于将这种电组件作为其一部分的信息处理系统。

公开(公告)号：US07627947B2

公开(公告)日：2009-12-08

申请号：US11797232

申请日：2007-05-02

申请人： Thomas J. Davis ,  Subahu D. Desai ,  John M. Lauffer ,  James J. McNamara, Jr. ,  Voya R. Markovich

发明人： Thomas J. Davis ,  Subahu D. Desai ,  John M. Lauffer ,  James J. McNamara, Jr. ,  Voya R. Markovich

IPC分类号： H05K3/10 ,  H01R12/04

CPC分类号： H05K3/429 ,  H05K3/0032 ,  H05K3/0038 ,  H05K3/427 ,  H05K3/445 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0143 ,  H05K2203/0554 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of making a multilayered circuitized substrate in which a continuous process is used to form electrically conductive layers which each will form part of a sub-composite. The sub-composites are then aligned such that openings within the conductive layers are also aligned, the sub-composites are then bonded together, and a plurality of holes are then laser drilled through the entire thickness of the bonded structure. The dielectric layers used in the sub-composites do not include continuous or semi-continuous fibers therein, thus expediting hole formation there-through.

摘要翻译： 制造多层电路化基板的方法，其中使用连续工艺来形成每个将形成子复合材料的一部分的导电层。 然后对准次级复合材料，使得导电层内的开口也对准，然后将该次级复合材料结合在一起，然后在结合结构的整个厚度上激光钻出多个孔。 在次级复合材料中使用的电介质层不包括其中的连续或半连续的纤维，因此加速了孔的形成。

公开(公告)号：US20090178273A1

公开(公告)日：2009-07-16

申请号：US12007704

申请日：2008-01-15

申请人： John M. Lauffer

发明人： John M. Lauffer

IPC分类号： H05K3/36

CPC分类号： H05K1/142 ,  H05K1/183 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4694 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061 ,  H05K2203/068 ,  Y10T29/49126

摘要： A method of forming a circuitized substrate assembly in which at least two adjacent and contiguous circuitized substrates have at least one, and possibly a second, circuitized substrate positioned thereon and bonded thereto to form a combined circuitized substrate assembly. The substrates each include at least one conductive thru-hole therein such that the bonding will cause respective pairs (at least one pair if only three substrates are used) of the thru-holes to align and become electrically coupled, thereby forming at least one and preferably more electrical circuit paths through the combined assembly to electrically couple electrical components positioned on selected ones of the circuitized substrates.

摘要翻译： 一种形成电路化的基板组件的方法，其中至少两个相邻和连续的电路化基板具有位于其上的至少一个并且可能是第二个经电路化的基板并与其结合以形成组合的电路化基板组件。 基板各自在其中包括至少一个导电通孔，使得接合将引起通孔的相应对（至少一对，如果仅使用三个基板），以对准和变得电耦合，从而形成至少一个和 优选地，更多的电路通过组合组件以电耦合位于所选电路化基板上的电气部件。