公开(公告)号：US20170133460A1

公开(公告)日：2017-05-11

申请号：US14936651

申请日：2015-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-I Wu ,  I-cheng Hu ,  Yu-Shu Lin ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Kun-Hsin Chen ,  Neng-Hui Yang ,  Shu-Yen Chan

IPC: H01L29/06 ,  H01L21/3065 ,  H01L29/16 ,  H01L21/283 ,  H01L29/423 ,  H01L21/306 ,  H01L21/225

CPC classification number: H01L21/283 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a method for forming a semiconductor structure, including: first, a substrate is provided. Next, at least two gate structures are formed on the substrate, each gate structure including two spacers disposed on two sides of the gate structure. Afterwards, a dry etching process is performed to remove parts of the substrate, so as to form a recess in the substrate, and a wet etching process is performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively. In addition, parts of the spacer are also removed through the wet etching process, and each spacer includes a rounding corner disposed on a bottom surface of the spacer.

公开(公告)号：US20170133287A1

公开(公告)日：2017-05-11

申请号：US14933107

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Dieter Lipp ,  Stefan Richter

IPC: H01L21/66 ,  H01L21/283 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/283 ,  H01L21/02488 ,  H01L22/34 ,  H01L29/0653 ,  H01L29/78

Abstract: The present disclosure provides a test structure which includes an SOI substrate having an active semiconductor layer, a buried insulating material layer, and a base substrate, wherein the active semiconductor layer is formed on the buried insulating material layer, which, in turn, is formed on the base substrate. The test structure further includes a contact which is formed on the active semiconductor layer and electrically coupled to the active semiconductor layer. Herein, the contact has a tip portion extending through the active semiconductor layer into the buried insulating material layer.

公开(公告)号：US20170125542A1

公开(公告)日：2017-05-04

申请号：US15406096

申请日：2017-01-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. CHOU ,  Arvind KUMAR ,  Chung-Hsun LIN ,  Shreesh NARASIMHA ,  Claude ORTOLLAND ,  Jonathan T. SHAW

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US20170125301A1

公开(公告)日：2017-05-04

申请号：US15358061

申请日：2016-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： WEI-SHUO HO ,  TSUNG-YU CHIANG ,  KUANG-HSIN CHEN

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/283 ,  H01L21/306 ,  H01L21/311 ,  H01L29/49 ,  H01L21/768 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324

CPC classification number: H01L21/823431 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/823456 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/518 ,  H01L29/6681 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate; patterning a first active region, a second active region and an isolation between the first active region and the second active region over the substrate; disposing an inter-level dielectric (ILD) over the substrate; forming a first gate extended over the first active region, the isolation and the second active region; and forming a second gate over the first active region and the second active region, wherein the second gate includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.

公开(公告)号：US20170104065A1

公开(公告)日：2017-04-13

申请号：US14948492

申请日：2015-11-23

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Robert H. Dennard ,  Zhen Zhang

IPC: H01L29/08 ,  H01L21/324 ,  H01L21/225 ,  H01L29/78 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02634 ,  H01L21/02694 ,  H01L21/2251 ,  H01L21/283 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a gate structure formed on the channel region. A first dual-layer source/drain region is on the first active region and a second dual-layer source/drain region is on the second active region. The first and second dual-layer source/drain regions include stacked layers formed of different semiconductor materials. A first extension region is embedded in the first active region and a second extension region is embedded in the second active region.

公开(公告)号：US09620428B2

公开(公告)日：2017-04-11

申请号：US15217777

申请日：2016-07-22

Applicant: Monolith Semiconductor Inc.

Inventor： Kevin Matocha ,  John Nowak ,  Kiran Chatty ,  Sujit Banerjee

IPC: H01L29/45 ,  H01L23/26 ,  H01L23/00 ,  H01L29/16 ,  H01L29/78 ,  H01L21/283 ,  H01L23/31 ,  H01L29/10 ,  H01L21/04 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L23/26 ,  H01L21/0445 ,  H01L21/0485 ,  H01L21/283 ,  H01L21/823475 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/564 ,  H01L24/05 ,  H01L29/0615 ,  H01L29/0843 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66893 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7811 ,  H01L29/7823 ,  H01L29/8083 ,  H01L29/872 ,  H01L2224/02166 ,  H01L2224/051 ,  H01L2224/05111 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0517 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/0519 ,  H01L2224/05567 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.

公开(公告)号：US20170098581A1

公开(公告)日：2017-04-06

申请号：US15383837

申请日：2016-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Shuo HO ,  Tsung-Yu CHIANG ,  Chia-Ming CHANG ,  Jyun-Ming LIN

IPC: H01L21/8234 ,  H01L21/027 ,  H01L27/088 ,  H01L21/768 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/823456 ,  H01L21/0273 ,  H01L21/28008 ,  H01L21/28123 ,  H01L21/283 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659

Abstract: Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.

公开(公告)号：US09607900B1

公开(公告)日：2017-03-28

申请号：US14850154

申请日：2015-09-10

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L27/01 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L29/66 ,  H01L21/283 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/201

CPC classification number: H01L21/823807 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0226 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/823814 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/201 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers of a first and a second material in a stack on a substrate; forming a first trench(es) and a second trench(es) in the stack; laterally etching the layer of the second material selectively within the first trench(es) to form first cavities in the layer; growing a first epitaxial material within the first trench(es) filling the first cavities; laterally etching the layer of the second material selectively within the second trench(es) to form second cavities in the layer; growing a second epitaxial material within the second trench(es) filling the second cavities, wherein the first epitaxial material in the first cavities and the second epitaxial material in the second cavities are the hybrid nanowires. A nanowire FET device and method for formation thereof are also provided.

公开(公告)号：US20170084623A1

公开(公告)日：2017-03-23

申请号：US15056465

申请日：2016-02-29

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Rahul SHARANGPANI ,  Somesh PERI ,  Raghuveer S. MAKALA ,  Yanli ZHANG

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/283 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/42328

Abstract: Metal floating gate electrodes can be formed for a three-dimensional memory device by forming a memory opening having lateral recesses at levels of spacer material layers between insulating layers, depositing a continuous metal layer, and inducing diffusion and agglomeration of the metal into the lateral recesses to form discrete metal portions employing an anneal process. The metallic material can migrate and form the discrete metal portions due to surface tension, which operates to minimize the surface area of the metallic material. Optionally, two or more continuous metal layers can be employed to form discrete metal portions including at least two metals. Optionally, a selective metal deposition process can be performed to deposit additional metal portions including a different metallic material on the discrete metal portions. The metal floating gate electrodes can be formed without employing an etch process. A tunneling dielectric layer and a semiconductor channel can be subsequently formed.

公开(公告)号：US20170084601A1

公开(公告)日：2017-03-23

申请号：US15268773

申请日：2016-09-19

Applicant: Silergy Semiconductor Technology (Hangzhou) LTD

Inventor： Fei Yao ,  Shijun Wang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L21/761 ,  H01L21/283 ,  H01L29/866 ,  H01L23/528

CPC classification number: H01L27/0255 ,  H01L21/283 ,  H01L21/761 ,  H01L23/5283 ,  H01L29/0646 ,  H01L29/66106 ,  H01L29/866

Abstract: A transient voltage suppressor can include: a semiconductor substrate; a first buried layer of a first type formed in and on the semiconductor substrate; a second buried layer of a second type formed in a first region of the first buried layer; a first epitaxial region of the second type formed on the second buried layer and a second epitaxial region of the first type formed on a second region of the first buried layer; a first doped region of the first type formed in the first epitaxial region and a second doped region of the second type formed in the second epitaxial region; a conductive channel extending from a surface of the second epitaxial region into the first buried layer; and a first electrode connected to the conductive channel, a second electrode connected to the first doped region, and a third electrode connected to the second doped region.