公开(公告)号：US09478509B2

公开(公告)日：2016-10-25

申请号：US14198711

申请日：2014-03-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ronald G. Filippi ,  Erdem Kaltalioglu ,  Andrew T. Kim ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/03426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/08145 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/1317 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13184 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2924/05042 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2224/034

Abstract: The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

Abstract translation: 本发明一般涉及倒装芯片技术，更具体地说，涉及用于在半导体结构上制造机械锚定的控制崩溃芯片连接（C 4）焊盘的方法和结构。 在一个实施例中，公开了一种方法，其可以包括形成具有延伸到半导体结构中的一个或多个锚定区域的焊盘，并且可能在温度波动期间阻止焊盘与TSV物理分离。

公开(公告)号：US09430605B2

公开(公告)日：2016-08-30

申请号：US14825856

申请日：2015-08-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Wei Lai ,  Ming-Che Ho ,  Tzong-Hann Yang ,  Chien Rhone Wang ,  Chia-Tung Chang ,  Hung-Jui Kuo ,  Chung-Shi Liu

IPC: H01L21/44 ,  G06F17/50 ,  H01L23/488 ,  H01L23/00

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L23/488 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

公开(公告)号：US09412709B2

公开(公告)日：2016-08-09

申请号：US13898949

申请日：2013-05-21

Applicant: Sheila F. Chopin ,  Min Ding ,  Varughese Mathew ,  Scott S. Roth

Inventor： Sheila F. Chopin ,  Min Ding ,  Varughese Mathew ,  Scott S. Roth

IPC: H01L21/56 ,  H01L21/44 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/02 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/03005 ,  H01L2224/03009 ,  H01L2224/03015 ,  H01L2224/03019 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05565 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/73265 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/365 ,  H01L2924/3651 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

Abstract translation: 通过在集成电路器件的外表面上形成导电焊盘来形成封装的半导体器件，在导电焊盘上方形成钝化层，在导电焊盘上的接合区域上去除钝化层的一部分，形成牺牲阳极 在围绕结合区域的周边的大部分周围，在接合区域中形成导电结合，以及在导电接合周围形成封装材料和牺牲阳极的暴露部分。

公开(公告)号：US20160020184A1

公开(公告)日：2016-01-21

申请号：US14526073

申请日：2014-10-28

Applicant: SK hynix Inc.

Inventor： Jin Woo PARK ,  Sung Su PARK ,  Bae Yong KIM

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/051 ,  H01L2224/05138 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01014 ,  H01L2924/012

Abstract: A semiconductor device includes a chip body having an uneven surface including at least two regions at different levels from one another, a through electrode penetrating the chip body and having an end which is exposed by the uneven surface of the chip body, a passivation layer disposed on the uneven surface of the chip body, and a bump disposed on the passivation layer and the exposed end of the through electrode and overlapping with the uneven surface of the chip body.

Abstract translation: 一种半导体器件包括：芯片本体，具有包括彼此不同的至少两个区域的不平坦表面;穿透芯片本体并具有由芯片体的不平坦表面露出的端部的贯通电极，设置有钝化层 并且设置在钝化层和通孔的露出端上并与芯片体的不平坦表面重叠的凸起。

公开(公告)号：US09224704B2

公开(公告)日：2015-12-29

申请号：US13219099

申请日：2011-08-26

Applicant: Didier Landru

Inventor： Didier Landru

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/30 ,  H01L21/46 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0332 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05006 ,  H01L2224/05082 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05187 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05576 ,  H01L2224/05578 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/04941 ,  H01L2924/00

Abstract: The present invention relates to a process for realizing a connecting structure in a semiconductor substrate, and the semiconductor substrate realized accordingly. The semiconductor substrate has at least a first surface, and is foreseen for a 3D integration with a second substrate along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value. This process includes growing a diffusion barrier structure for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, wherein a first end surface, being the most outward surface of the diffusion barrier structure and being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure can have a length, in the direction of the lateral misalignment, the length being dependent on the misalignment value, wherein the length of the diffusion barrier structure is chosen such that in a 3D integrated structure a diffusion of elements out of a conductive layer of the second substrate is prevented in the integrated state.

Abstract translation: 本发明涉及实现半导体衬底中的连接结构的方法，并且相应地实现了半导体衬底。 半导体衬底具有至少第一表面，并且预期用于沿着第一表面与第二衬底的3D集成，其中3D积分在具有未对准值的至少一个维度中受到横向错位。 该方法包括生长扩散阻挡结构，用于防止元件从导电层扩散到半导体衬底的其余部分中，其中第一端面是扩散阻挡结构的最外表面，并且基本平行于第一表面 沿垂直于第一表面的方向并且从衬底朝着第一表面延伸的扩散阻挡结构的长度可以在横向不对准的方向上具有取决于不对准值的长度，其中， 扩散阻挡结构被选择为使得在3D集成结构中，元件在第二基板的导电层中的扩散在集成状态下被阻止。

公开(公告)号：US20150347663A1

公开(公告)日：2015-12-03

申请号：US14825856

申请日：2015-08-13

Applicant: Taiwan Samiconductor Manufacturing Comapny, Ltd.

Inventor： Chih-Wei Lai ,  Ming-Che Ho ,  Tzong-Hann Yang ,  Chien Rhone Wang ,  Chia-Tung Chang ,  Hung-Jui Kuo ,  Chung-Shi Liu

IPC: G06F17/50 ,  H01L23/00

CPC classification number: G06F17/5077 ,  G06F17/5072 ,  H01L23/488 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

Abstract translation: 一种装置包括在包装部件的顶表面上的多个连接器。 多个连接器包括具有第一横向尺寸的第一连接器和具有第二横向尺寸的第二连接器。 第二横向尺寸大于第一横向尺寸。 第一和第二横向尺寸在平行于包装部件的主表面的方向上测量。

公开(公告)号：US09087732B1

公开(公告)日：2015-07-21

申请号：US14170824

申请日：2014-02-03

Applicant: Maxim Integrated Products, Inc.

Inventor： Yong L. Xu ,  Viren Khandekar ,  Yi-Sheng A. Sun ,  Arkadii V. Samoilov

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0239 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05172 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05563 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05672 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/1401 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2224/05552

Abstract: Wafer-level package (semiconductor) devices are described that have a pillar structure that extends at least partially into a solder bump to mitigate thermal stresses to the solder bump. In implementations, the wafer-level package device may comprise an integrated circuit chip having a surface and a solder bump disposed over the surface. The wafer-level package device may also include a pillar structure disposed over the surface that extends at least partially into the solder bump.

Abstract translation: 描述了晶片级封装（半导体）器件，其具有至少部分地延伸到焊料凸块中以减轻对焊料凸块的热应力的柱结构。 在实现中，晶片级封装器件可以包括具有设置在表面上的表面和焊料凸块的集成电路芯片。 晶片级封装器件还可以包括设置在表面上的至少部分地延伸到焊料凸块中的柱结构。

公开(公告)号：US09070747B2

公开(公告)日：2015-06-30

申请号：US14039384

申请日：2013-09-27

Applicant: FlipChip International, LLC

Inventor： Eugene A. Stout ,  Douglas M. Scott ,  Anthony P. Curtis ,  Theodore G. Tessier ,  Guy F. Burgess

IPC: H01L23/544 ,  H01L21/768 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/76837 ,  C25D5/022 ,  C25D7/123 ,  H01L21/76873 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/034 ,  H01L2224/0401 ,  H01L2224/11462 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Structures and methods provide a dielectric bridge for use in electroplating. A method comprises: providing a semiconductor wafer with a plurality of die, wherein a first die is adjacent to a second die, and the first die and second die are separated by a dicing street area; forming a patterned dielectric layer overlying the semiconductor wafer, the dielectric layer including a dielectric bridge that crosses the dicing street area; forming a conductive layer (e.g., a metal seed layer) overlying the dielectric layer, wherein a portion of the conductive layer is overlying the dielectric bridge to provide a current pathway from the first die to the second die; and electroplating targeted areas of the conductive layer by providing current to the second die using the current pathway. Other such bridges formed from the dielectric layer provide current pathways to other die on the wafer.

Abstract translation: 结构和方法提供用于电镀的介电桥。 一种方法包括：提供具有多个裸片的半导体晶片，其中第一裸片与第二裸片相邻，并且第一裸片和第二裸片由切割街道区域分开; 形成覆盖所述半导体晶片的图案化电介质层，所述电介质层包括穿过所述切割街道区域的电介质桥; 形成覆盖所述电介质层的导电层（例如，金属种子层），其中所述导电层的一部分覆盖在所述电介质桥上，以提供从所述第一管芯到所述第二管芯的电流通路; 以及通过使用电流路径向第二管芯提供电流来电镀导电层的目标区域。 由电介质层形成的其它这样的桥提供电流通向晶片上的其它晶粒。

公开(公告)号：US20150162257A1

公开(公告)日：2015-06-11

申请号：US14097433

申请日：2013-12-05

Applicant: Yan Xun Xue

Inventor： Yan Xun Xue

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/304 ,  H01L21/768 ,  H01L21/56 ,  H01L21/78 ,  H01L23/48

CPC classification number: H01L23/535 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/03 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05025 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Abstract translation: 一种用于提供具有增加的接触焊盘区域的晶片级封装的方法，包括以下步骤：在晶片顶表面上形成第一封装层，研磨晶片背面并蚀刻通孔，沉积金属以填充通孔并覆盖晶片背面， 从晶片背面切割晶片，形成分开每个芯片的多个沟槽，然后沉积填充沟槽并覆盖晶片背面金属的第二封装层，减小第一封装层厚度以露出填充凹槽的第二封装层并形成多个 接触垫重叠在第一包装层上，然后切割槽中的第二包装层以形成单个包装。

公开(公告)号：US20150155224A1

公开(公告)日：2015-06-04

申请号：US14465884

申请日：2014-08-22

Applicant: Mitsubishi Electric Corporation

Inventor： Hidetoshi Koyama

IPC: H01L23/482 ,  H01L23/48

CPC classification number: H01L23/4827 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/039 ,  H01L2224/04026 ,  H01L2224/05005 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05116 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05179 ,  H01L2224/05187 ,  H01L2224/05561 ,  H01L2224/05564 ,  H01L2224/05644 ,  H01L2224/29022 ,  H01L2224/291 ,  H01L2224/29144 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/054 ,  H01L2924/01028 ,  H01L2924/01078 ,  H01L2924/0544 ,  H01L2924/01082 ,  H01L2924/05341 ,  H01L2924/0539 ,  H01L2924/01027 ,  H01L2924/0105 ,  H01L2224/034

Abstract: A semiconductor device includes a semiconductor substrate, a first metal layer, a barrier metal layer, and a second metal layer. The semiconductor substrate includes a front surface and a back surface. A semiconductor element and an electrode of the semiconductor element are located on the front surface. An opening in the back surface reaches a lower surface of the electrode, and the opening is defined by a side surface and a bottom surface. The first metal layer covers the side surface and the bottom surface. The barrier metal layer covers the first metal layer in the opening The second metal layer is in contact with solder in the opening and is closer to the electrode than parts of the barrier metal layer. The second metal layer is laminated on the barrier metal layer and covers at least a part of the barrier metal layer in the opening

Abstract translation: 半导体器件包括半导体衬底，第一金属层，阻挡金属层和第二金属层。 半导体衬底包括前表面和后表面。 半导体元件的半导体元件和电极位于前表面。 后表面的开口到达电极的下表面，并且开口由侧表面和底表面限定。 第一金属层覆盖侧表面和底表面。 阻挡金属层覆盖开口中的第一金属层。第二金属层与开口中的焊料接触，并且比阻挡金属层的部分更靠近电极。 第二金属层被层压在阻挡金属层上并且覆盖开口中的阻挡金属层的至少一部分