公开(公告)号：US09190375B2

公开(公告)日：2015-11-17

申请号：US14248373

申请日：2014-04-09

Applicant: International Business Machines Corporation

Inventor： Stephen P. Ayotte ,  Sebastien S. Quesnel ,  Glen E. Richard ,  Timothy D. Sullivan ,  Timothy M. Sullivan

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/0516 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05686 ,  H01L2224/10156 ,  H01L2224/10175 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81222 ,  H01L2224/81815 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A method of applying inductive heating to join an integrated circuit chip to an electrical substrate using solder bumps including applying a magnetic field to a magnetic liner in thermal contact with a solder bump on the integrated circuit chip. The magnetic field causes Joule heating in the magnetic liner sufficient to melt the solder bump, which has a lower portion embedded in a first dielectric layer and an upper portion at least partially embedded in a second dielectric layer. The lower portion is in electrical contact with a conductive pad, the first dielectric layer is above the conductive pad and the second dielectric layer is on top of the first dielectric layer. The duration of application of the magnetic field is controlled to achieve a joining temperature that is approximately halfway between the storage and operating temperatures of the integrated circuit chip.

Abstract translation: 一种施加感应加热以将集成电路芯片连接到电气基板的方法，其使用焊料凸块，包括将磁场施加到与集成电路芯片上的焊料凸块热接触的磁性衬垫。 磁场使得磁性衬垫中的焦耳加热足以熔化焊料凸块，焊料凸块具有嵌入在第一电介质层中的下部和至少部分地嵌入第二介电层中的上部。 下部与导电焊盘电接触，第一介电层位于导电焊盘的上方，第二介电层位于第一介质层的顶部。 控制施加磁场的持续时间以实现大约在集成电路芯片的存储和工作温度之间的接合温度。

公开(公告)号：US09153555B2

公开(公告)日：2015-10-06

申请号：US11678599

申请日：2007-02-25

Applicant: Jin-Yuan Lee ,  Ying-Chih Chen ,  Mou-Shiung Lin

Inventor： Jin-Yuan Lee ,  Ying-Chih Chen ,  Mou-Shiung Lin

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L24/48 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/854 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/04953 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

公开(公告)号：US20150262953A1

公开(公告)日：2015-09-17

申请号：US14209118

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Li-Guo LEE ,  Yi-Chen LIU ,  Yung-Sheng LIU ,  Yi-Jen LAI ,  Chun-Jen CHEN ,  Hsi-Kuei CHENG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11821 ,  H01L2224/11827 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13693 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/01079 ,  H01L2224/1182 ,  H01L2924/00012 ,  H01L2924/04953 ,  H01L2924/01047

Abstract: A semiconductor device structure and a manufacturing method are provided. The method includes forming a conductive pillar over a semiconductor substrate. The method also includes forming a solder layer over the conductive pillar. The method further includes forming a water-soluble flux over the solder layer. In addition, the method includes reflowing the solder layer to form a solder bump over the conductive pillar and form a sidewall protection layer over a sidewall of the conductive pillar during the solder layer is reflowed.

Abstract translation: 提供半导体器件结构和制造方法。 该方法包括在半导体衬底上形成导电柱。 该方法还包括在导电柱上形成焊料层。 该方法还包括在焊料层上形成水溶性助焊剂。 此外，该方法包括回流焊料层以在导电柱上形成焊料凸块，并且在焊料层回流期间在导电柱的侧壁上形成侧壁保护层。

公开(公告)号：US09123788B2

公开(公告)日：2015-09-01

申请号：US14480439

申请日：2014-09-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Hong Cha ,  Chita Chuang ,  Yao-Chun Chuang ,  Hao-Juin Liu ,  Tsung-Hsien Chiang ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/13 ,  H01L21/76897 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13601 ,  H01L2224/141 ,  H01L2224/14154 ,  H01L2224/14177 ,  H01L2224/145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/171 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

Abstract translation: 所描述的实施例提供了在基本上面向封装结构的中心的铜柱的侧面上没有焊料润湿的封装结构的边缘附近的细长结合结构。 焊接润湿发生在这些结合结构的铜柱的另一侧。 细长结合结构被布置成不同的布置并且减小相邻结合结构之间短路的机会。 另外，细长的结合结构提高了可靠性。

公开(公告)号：US20150221611A1

公开(公告)日：2015-08-06

申请号：US14257833

申请日：2014-04-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shin-Puu Jeng ,  Wen-Chih Chiou ,  Tu-Hao Yu ,  Hung-Jung Tu ,  Yu-Liang Lin ,  Shih-Hui Wang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13811 ,  H01L2224/13816 ,  H01L2224/13839 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/80805 ,  H01L2224/81805 ,  H01L2224/83 ,  H01L2224/83192 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/151 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/161 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes coupling integrated circuit dies to a substrate, and disposing a molding material around the integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies.

Abstract translation: 公开了封装半导体器件和封装半导体器件的方法。 在一些实施例中，封装半导体器件的方法包括将集成电路管芯耦合到衬底，以及将模制材料设置在集成电路管芯周围。 盖层设置在成型材料和多个集成电路管芯之上。

公开(公告)号：US09093332B2

公开(公告)日：2015-07-28

申请号：US13023011

申请日：2011-02-08

Applicant: Tin-Hao Kuo ,  Yu-Feng Chen ,  Chen-Shien Chen ,  Chen-Hua Yu ,  Sheng-Yu Wu ,  Chita Chuang

Inventor： Tin-Hao Kuo ,  Yu-Feng Chen ,  Chen-Shien Chen ,  Chen-Hua Yu ,  Sheng-Yu Wu ,  Chita Chuang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/14141 ,  H01L2224/81192 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An elongated bump structure for semiconductor devices is provided. An uppermost protective layer has an opening formed therethrough. A pillar is formed within the opening and extending over at least a portion of the uppermost protective layer. The portion extending over the uppermost protective layer exhibits a generally elongated shape. In an embodiment, the position of the opening relative to the portion of the bump structure extending over the uppermost protective layer is such that a ratio of a distance from an edge of the opening to an edge of the bump is greater than or equal to about 0.2. In another embodiment, the position of the opening is offset relative to center of the bump.

Abstract translation: 提供了用于半导体器件的细长凸块结构。 最上面的保护层具有通过其形成的开口。 在该开口内形成一个支柱，并延伸至最上层保护层的至少一部分。 在最上保护层上延伸的部分呈现大致细长的形状。 在一个实施例中，开口相对于在最上保护层上延伸的凸起结构的部分的位置使得从开口的边缘到凸起的边缘的距离的比例大于或等于约 0.2。 在另一个实施例中，开口的位置相对于凸块的中心偏移。

公开(公告)号：US09087885B2

公开(公告)日：2015-07-21

申请号：US14247234

申请日：2014-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wook Ji ,  Yeong-Lyeol Park ,  Hyoung-Yol Mun ,  In-Kyum Lee

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2224/02311 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/06182 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01028 ,  H01L2924/01079

Abstract: Provided is a method of fabricating a semiconductor device. In one embodiment, the method includes forming at least one unit device in a substrate and on a front side of the substrate, forming a through-silicon via (TSV) structure apart from the at least one unit device to substantially vertically penetrate the substrate, the TSV structure having a back end including a concave portion, forming an internal circuit on the front side of the substrate and a front end of the TSV structure to be electrically connected to the at least one unit device and the front end of the TSV structure, forming a front side bump on the front side of the substrate to be electrically connected to the front end of the TSV structure, forming a redistribution layer on a back side of the substrate to be electrically connected to the back end of the TSV structure, and forming a back side bump to be electrically connected to the redistribution layer.

Abstract translation: 提供一种制造半导体器件的方法。 在一个实施例中，该方法包括在衬底中和衬底的正面上形成至少一个单元器件，形成远离至少一个单元器件的贯穿硅通孔（TSV）结构，以基本上垂直地穿透衬底， 所述TSV结构具有后端，所述后端包括凹部，在所述基板的前侧形成内部电路，并且所述TSV结构的前端电连接到所述至少一个单元装置和所述TSV结构的前端 在所述基板的前侧形成前侧凸块以与TSV结构的前端电连接，在所述基板的背侧形成再分配层，以与TSV结构的后端电连接， 以及形成背面凸块以与再分布层电连接。

公开(公告)号：US20150194397A1

公开(公告)日：2015-07-09

申请号：US14657789

申请日：2015-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Yu-Wen Liu

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of forming a bond pad structure is provided. The method includes forming a first conductive layer over a substrate and depositing a first dielectric layer over the first conductive layer. The first dielectric layer is patterned to form a contiguous planar path substantially parallel to a top surface of the substrate. Patterning the first dielectric layer includes defining a dielectric region of the first dielectric layer surrounded by a portion of the contiguous planar path, and forming a first via hole in the dielectric region. The contiguous planar path and the via hole are filled with a conductive material. The conductive material in the contiguous planar path forms a second conductive layer, and the contiguous planar path extends from a first lateral side wall of the second conductive layer to a second lateral sidewall of the second conductive layer. A bond pad is formed over the second conductive layer, and the bond pad is electrically connected to the second conductive layer.

Abstract translation: 提供一种形成接合焊盘结构的方法。 该方法包括在衬底上形成第一导电层并在第一导电层上沉积第一介电层。 图案化第一电介质层以形成基本上平行于衬底的顶表面的邻接平面路径。 对第一电介质层进行图案化包括限定由邻接平面路径的一部分包围的第一介电层的电介质区域，以及在电介质区域中形成第一通孔。 邻接的平面路径和通孔填充有导电材料。 邻接平面路径中的导电材料形成第二导电层，并且邻接的平面路径从第二导电层的第一横向侧壁延伸到第二导电层的第二横向侧壁。 在第二导电层上形成接合焊盘，并且接合焊盘与第二导电层电连接。

公开(公告)号：US20150187714A1

公开(公告)日：2015-07-02

申请号：US14140796

申请日：2013-12-26

Applicant: GLOBAL FOUNDRIES Singapore Pte. Ltd.

Inventor： Mahesh Anant Bhatkar ,  Tan Juan Boon ,  Liu Wei ,  Oswald Jens

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03831 ,  H01L2224/0384 ,  H01L2224/0401 ,  H01L2224/05085 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11616 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13647 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/384 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: Integrated circuits including copper pillar structures and methods for fabricating the same are disclosed. In one exemplary embodiment, an integrated circuit includes a last metal layer and a passivation layer disposed over the last metal layer, both the last metal and passivation layers being disposed over an integrated circuit active device on a semiconductor substrate. The integrated circuit further includes a copper pillar structure disposed partially within a first portion of the passivation layer and immediately over the last metal layer. The first portion of the passivation layer is defined by first and second sidewalls of the passivation layer and an upper surface of the last metal layer. The copper pillar structure includes a liner formed along the first and second sidewalls and over the upper surface of the last metal and a copper material within the liner. The copper pillar structure, including both the liner and the copper material within the liner, further extends to a height above an upper surface of the passivation layer.

Abstract translation: 公开了包括铜柱结构的集成电路及其制造方法。 在一个示例性实施例中，集成电路包括最后的金属层和设置在最后一个金属层上的钝化层，最后的金属层和钝化层都设置在半导体衬底上的集成电路有源器件上。 集成电路还包括铜柱结构，该铜柱结构部分地设置在钝化层的第一部分内并且紧邻最后的金属层。 钝化层的第一部分由钝化层的第一侧壁和第二侧壁以及最后一个金属层的上表面限定。 铜柱结构包括沿着第一和第二侧壁以及在最后金属的上表面上形成的衬垫和衬里内的铜材料。 包括内衬中的衬垫和铜材料的铜柱结构进一步延伸到钝化层的上表面上方的高度。

公开(公告)号：US20150162291A1

公开(公告)日：2015-06-11

申请号：US14098218

申请日：2013-12-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHIA-CHUN MIAO ,  SHIH-WEI LIANG ,  KAI-CHIANG WU ,  YEN-PING WANG

IPC: H01L23/00

CPC classification number: H01L23/564 ,  H01L23/16 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/03828 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05687 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/118 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81466 ,  H01L2224/81471 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/013 ,  H01L2224/81 ,  H01L2224/03

Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor device has a metal structure over the semiconductor substrate. The metal structure is configured to receive a bump. The semiconductor device further has a conductive trace between the semiconductor substrate and the metal structure. The conductive trace is configured to connect to a power source. When an electric current from the power source passes through the conductive trace, an electromagnetic field is generated at the conductive trace. The position of the bump is adjusted in response to the electromagnetic field.

Abstract translation: 提供了具有半导体衬底的半导体器件。 半导体器件在半导体衬底上具有金属结构。 金属结构构造成接收凸起。 半导体器件还在半导体衬底和金属结构之间具有导电迹线。 导电迹线被配置为连接到电源。 当来自电源的电流通过导电迹线时，在导电迹线处产生电磁场。 凸起的位置响应于电磁场而被调节。