公开(公告)号：US20110012263A1

公开(公告)日：2011-01-20

申请号：US12814472

申请日：2010-06-13

申请人： Hanae HATA ,  Masato Nakamura ,  Nobuhiro Kinoshita ,  Jumpei Konno ,  Chiko Yorita

发明人： Hanae HATA ,  Masato Nakamura ,  Nobuhiro Kinoshita ,  Jumpei Konno ,  Chiko Yorita

IPC分类号： H01L23/538 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L24/16 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/45144 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48

摘要： In order to achieve the highly reliable and highly functional semiconductor device capable of the high-speed transmission by stacking thin chips and substrates, a connecting process and a connecting structure capable of making a solid connection at a low temperature with a low load and maintaining the shape of a connecting portion even if the connecting portion is heated in the stacking process and the subsequent mounting process are provided. In a semiconductor device in which semiconductor chips or wiring boards on which semiconductor chips are mounted are stacked, a connecting structure between electrodes of the stacked semiconductor chips or wiring boards includes a pair of electrodes mainly made of Cu and a solder layer made of Sn—In based alloy sandwiched between the electrodes, and Sn—Cu—Ni intermetallic compounds are dispersed in the solder layer.

摘要翻译： 为了实现能够通过堆叠薄片和衬底的高速传输的高可靠性和高功能的半导体器件，能够在低负载下实现牢固连接的连接工艺和连接结构，并且保持 即使在堆叠过程中加热连接部分并且提供随后的安装过程，连接部分的形状也是如此。 在其中堆叠半导体芯片的半导体芯片或布线板堆叠的半导体器件中，堆叠的半导体芯片或布线板的电极之间的连接结构包括主要由Cu制成的一对电极和由Sn- 夹在电极之间的基体合金和Sn-Cu-Ni金属间化合物分散在焊料层中。

公开(公告)号：US08633103B2

公开(公告)日：2014-01-21

申请号：US12814472

申请日：2010-06-13

申请人： Hanae Hata ,  Masato Nakamura ,  Nobuhiro Kinoshita ,  Jumpei Konno ,  Chiko Yorita

发明人： Hanae Hata ,  Masato Nakamura ,  Nobuhiro Kinoshita ,  Jumpei Konno ,  Chiko Yorita

IPC分类号： H01L21/60 ,  H01L23/488

CPC分类号： H01L24/11 ,  H01L24/16 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/45144 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48

摘要： In order to achieve the highly reliable and highly functional semiconductor device capable of the high-speed transmission by stacking thin chips and substrates, a connecting process and a connecting structure capable of making a solid connection at a low temperature with a low load and maintaining the shape of a connecting portion even if the connecting portion is heated in the stacking process and the subsequent mounting process are provided. In a semiconductor device in which semiconductor chips or wiring boards on which semiconductor chips are mounted are stacked, a connecting structure between electrodes of the stacked semiconductor chips or wiring boards includes a pair of electrodes mainly made of Cu and a solder layer made of Sn—In based alloy sandwiched between the electrodes, and Sn—Cu—Ni intermetallic compounds are dispersed in the solder layer.

摘要翻译： 为了实现能够通过堆叠薄片和衬底的高速传输的高可靠性和高功能的半导体器件，能够在低负载下实现牢固连接的连接工艺和连接结构，并且保持 即使在堆叠过程中加热连接部分并且提供随后的安装过程，连接部分的形状也是如此。 在其中堆叠半导体芯片的半导体芯片或布线板堆叠的半导体器件中，堆叠的半导体芯片或布线板的电极之间的连接结构包括主要由Cu制成的一对电极和由Sn- 夹在电极之间的基体合金和Sn-Cu-Ni金属间化合物分散在焊料层中。

公开(公告)号：US20100309641A1

公开(公告)日：2010-12-09

申请号：US12521602

申请日：2008-03-21

申请人： Hanae Hata ,  Masato Nakamura ,  Masaki Nakanishi ,  Nobuhiro Kinoshita

发明人： Hanae Hata ,  Masato Nakamura ,  Masaki Nakanishi ,  Nobuhiro Kinoshita

IPC分类号： H05K7/00 ,  H01L23/488 ,  H01L21/60 ,  H05K1/09 ,  H05K3/10

CPC分类号： H01L23/49811 ,  H01L21/563 ,  H01L23/498 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/742 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05553 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/108 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/013 ,  H05K2203/049 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of forming narrow-pitch flip-chip bonding electrodes and wire bonding electrodes at the same time is provided so as to reduce the cost of a substrate. In addition, a low-cost solder supply method and a flip-chip bonding method to a thin Au layer are provided. A stacked layer of a Cu layer 23 and a Ni layer 24 is employed as the electrode structure, and an Au layer 25 is plated on the outer periphery thereof. In the flip-chip bonding, dissolution of Au into the solder is minimized by employing a metal jet system in the soldering to the electrodes, so that the formation of Sn—Au having a high melting point is prevented, and at the same time, the wire-bondable Au layer 25 is ensured.

摘要翻译： 同时提供形成窄间距倒装芯片接合电极和引线接合电极的方法，以降低基板的成本。 此外，提供了一种对于薄Au层的低成本焊料供给方法和倒装焊接方法。 使用Cu层23和Ni层24的堆叠层作为电极结构，在其外周面上镀Au层25。 在倒装芯片接合中，通过在焊接到电极中使用金属喷射系统来将Au溶解到焊料中被最小化，从而防止形成具有高熔点的Sn-Au，同时， 可焊接的Au层25被确保。

公开(公告)号：US07598121B2

公开(公告)日：2009-10-06

申请号：US11648646

申请日：2007-01-03

申请人： Nobuhiro Kinoshita ,  Jumpei Konno

发明人： Nobuhiro Kinoshita ,  Jumpei Konno

IPC分类号： H01L21/16

CPC分类号： H01L24/16 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75252 ,  H01L2224/81001 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83001 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/05599

摘要： A method of manufacturing a semiconductor device includes the steps of: grinding the rear surface of a semiconductor wafer to reduce its thickness; flattening the rear surface of the semiconductor wafer; dividing the semiconductor wafer into a plurality of semiconductor chips; forming gold bumps on the electrodes of the plurality of semiconductor chips; applying NCP to the front surface of a packaging board; and arranging the semiconductor chips over the packaging board through the NCP and pressing the back surfaces of the semiconductor chips to flip-chip bond the semiconductor chips to the packaging board. Therefore, it is possible to prevent NCP from rising onto the back surfaces of the semiconductor chips at the time of flip-chip bonding, whereby separation and cracking caused by a high-temperature treatment for assembly and mounting of a semiconductor device can be prevented and the reliability of the semiconductor device can be improved.

摘要翻译： 制造半导体器件的方法包括以下步骤：研磨半导体晶片的后表面以减小其厚度; 使半导体晶片的后表面变平; 将半导体晶片分成多个半导体芯片; 在所述多个半导体芯片的电极上形成金凸块; 将NCP施加到包装板的前表面; 并且通过NCP将半导体芯片布置在封装板上，并且按压半导体芯片的背面以将半导体芯片倒装芯片封装到封装板。 因此，可以防止在倒装芯片接合时NCP上升到半导体芯片的背面，由此能够防止由用于组装和安装半导体器件的高温处理引起的分离和破裂， 可以提高半导体器件的可靠性。

公开(公告)号：US08534532B2

公开(公告)日：2013-09-17

申请号：US13531566

申请日：2012-06-24

申请人： Jumpei Konno ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

发明人： Jumpei Konno ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

IPC分类号： H01L21/60

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

摘要： To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

摘要翻译： 为了提高半导体器件的可靠性，在倒装芯片接合工序中，事先将预先安装在突起电极的前端面上的焊料材料和预先施加在端子（接合引线）上的焊料材料） 加热并因此彼此集成并电连接。 端子包括具有第一宽度W1的宽部分（第一部分）和具有第二宽度W2的窄部分（第二部分）。 当焊料材料被加热时，布置在窄部分上的焊料材料的厚度变得小于布置在宽部分中的焊料材料的厚度。 然后，在倒装芯片接合工序中，将突出电极配置在狭窄部分上并粘合到窄部上。 因此，可以减少焊料材料的突出量。

公开(公告)号：US20130001274A1

公开(公告)日：2013-01-03

申请号：US13531566

申请日：2012-06-24

申请人： Jumpei KONNO ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

发明人： Jumpei KONNO ,  Takafumi Nishita ,  Nobuhiro Kinoshita ,  Kazunori Hasegawa ,  Michiaki Sugiyama

IPC分类号： B23K31/02 ,  B23K31/12

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

摘要： To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

摘要翻译： 为了提高半导体器件的可靠性，在倒装芯片接合工序中，事先将预先安装在突起电极的前端面上的焊料材料和预先施加在端子（接合引线）上的焊料材料） 加热并因此彼此集成并电连接。 端子包括具有第一宽度W1的宽部分（第一部分）和具有第二宽度W2的窄部分（第二部分）。 当焊料材料被加热时，布置在窄部分上的焊料材料的厚度变得小于布置在宽部分中的焊料材料的厚度。 然后，在倒装芯片接合工序中，将突出电极配置在狭窄部分上并粘合到窄部上。 因此，可以减少焊料材料的突出量。

公开(公告)号：US20050140023A1

公开(公告)日：2005-06-30

申请号：US11017077

申请日：2004-12-21

申请人： Nobuhiro Kinoshita ,  Jumpei Konno

发明人： Nobuhiro Kinoshita ,  Jumpei Konno

IPC分类号： H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L23/02 ,  H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18

CPC分类号： H01L24/16 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/75252 ,  H01L2224/81001 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83001 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/05599

摘要： A method of manufacturing a semiconductor device, includes the steps of: grinding the rear surface of a semiconductor wafer to reduce its thickness; flattening the rear surface of the semiconductor wafer; dividing the semiconductor wafer into a plurality of semiconductor chips; forming gold bumps on the electrodes of the plurality of semiconductor chips; applying NCP to the front surface of a packaging board; and arranging the semiconductor chips over the packaging board through the NCP and pressing the back surfaces of the semiconductor chips to flip-chip bond the semiconductor chips to the packaging board. Therefore, it is possible to prevent NCP from rising onto the back surfaces of the semiconductor chips at the time of flip-chip bonding, whereby separation and cracking caused by a high-temperature treatment for assembly and mounting of a semiconductor device can be prevented and the reliability of the semiconductor device can be improved.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：研磨半导体晶片的后表面以减小其厚度; 使半导体晶片的后表面变平; 将半导体晶片分成多个半导体芯片; 在所述多个半导体芯片的电极上形成金凸块; 将NCP施加到包装板的前表面; 并且通过NCP将半导体芯片布置在封装板上，并且按压半导体芯片的背面以将半导体芯片倒装芯片封装到封装板。 因此，可以防止在倒装芯片接合时NCP上升到半导体芯片的背面，由此能够防止由半导体器件的组装和安装的高温处理引起的分离和破裂， 可以提高半导体器件的可靠性。

公开(公告)号：US20150236003A1

公开(公告)日：2015-08-20

申请号：US14404099

申请日：2012-09-14

申请人： Jumpei Konno ,  Takafumi Nishita ,  Kenji Sakata ,  Nobuhiro Kinoshita ,  Michiaki Sugiyama ,  Tsuyoshi Kida ,  Yoshihiro Ono

发明人： Jumpei Konno ,  Takafumi Nishita ,  Kenji Sakata ,  Nobuhiro Kinoshita ,  Michiaki Sugiyama ,  Tsuyoshi Kida ,  Yoshihiro Ono

IPC分类号： H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/07 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/27312 ,  H01L2224/27334 ,  H01L2224/2741 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/29012 ,  H01L2224/29015 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/753 ,  H01L2224/75315 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83001 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8321 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/83906 ,  H01L2224/83907 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92242 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/11 ,  H01L21/304 ,  H01L2224/03 ,  H01L21/78 ,  H01L2221/68381 ,  H01L21/4825 ,  H01L2224/27 ,  H01L2924/01047

摘要： A method of manufacturing a semiconductor device obtained by laminating a first semiconductor chip and a second semiconductor chip with different planar sizes when seen in a plan view on a wiring board via an adhesive material, in which the second semiconductor chip with a relatively larger planar size is mounted on the first semiconductor chip with a relatively smaller planar size. Also, after the first and second semiconductor chips are mounted, the first and second semiconductor chips are sealed with resin. Here, before sealing with the resin, a gap between the second semiconductor chip and the wiring board is previously sealed with the adhesive material used when the first and second semiconductor chips are mounted.

摘要翻译： 一种制造半导体器件的方法，所述半导体器件通过层叠具有不同平面尺寸的第一半导体芯片和第二半导体芯片的方法，所述半导体器件和第二半导体芯片在通过粘合材料在布线板上的平面图中看到，其中具有相对较大的平面尺寸 以相对较小的平面尺寸安装在第一半导体芯片上。 此外，在安装第一和第二半导体芯片之后，用树脂密封第一和第二半导体芯片。 这里，在用树脂密封之前，当安装第一和第二半导体芯片时，使用所使用的粘合剂材料预先密封第二半导体芯片和布线板之间的间隙。

公开(公告)号：US20070111384A1

公开(公告)日：2007-05-17

申请号：US11648646

申请日：2007-01-03

申请人： Nobuhiro Kinoshita ,  Jumpei Konno

发明人： Nobuhiro Kinoshita ,  Jumpei Konno

IPC分类号： H01L21/00

CPC分类号： H01L24/16 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75252 ,  H01L2224/81001 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83001 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/05599

摘要： A method of manufacturing a semiconductor device includes the steps of: grinding the rear surface of a semiconductor wafer to reduce its thickness; flattening the rear surface of the semiconductor wafer; dividing the semiconductor wafer into a plurality of semiconductor chips; forming gold bumps on the electrodes of the plurality of semiconductor chips; applying NCP to the front surface of a packaging board; and arranging the semiconductor chips over the packaging board through the NCP and pressing the back surfaces of the semiconductor chips to flip-chip bond the semiconductor chips to the packaging board. Therefore, it is possible to prevent NCP from rising onto the back surfaces of the semiconductor chips at the time of flip-chip bonding, whereby separation and cracking caused by a high-temperature treatment for assembly and mounting of a semiconductor device can be prevented and the reliability of the semiconductor device can be improved.

摘要翻译： 制造半导体器件的方法包括以下步骤：研磨半导体晶片的后表面以减小其厚度; 使半导体晶片的后表面变平; 将半导体晶片分成多个半导体芯片; 在所述多个半导体芯片的电极上形成金凸块; 将NCP施加到包装板的前表面; 并且通过NCP将半导体芯片布置在封装板上，并且按压半导体芯片的背面以将半导体芯片倒装芯片封装到封装板。 因此，可以防止在倒装芯片接合时NCP上升到半导体芯片的背面，由此能够防止由用于组装和安装半导体器件的高温处理引起的分离和破裂， 可以提高半导体器件的可靠性。

公开(公告)号：US20060030075A1

公开(公告)日：2006-02-09

申请号：US11187981

申请日：2005-07-25

申请人： Michiaki Sugiyama ,  Nobuhiro Kinoshita ,  Junpei Konno

发明人： Michiaki Sugiyama ,  Nobuhiro Kinoshita ,  Junpei Konno

IPC分类号： H01L21/48

CPC分类号： H01L24/32 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/29 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2203/043 ,  H05K2203/046 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In the assembly of a semiconductor device, improvement in the reliability of flip chip bonding is aimed at. By forming a dummy terminal in the end portion of the row of a plurality of terminals for a flip chip in the package substrate, the flow of flux or solder can be suppressed with the dummy terminal, and a solder layer can be formed on the plurality of terminals for a flip chip. Thereby, the thickness of the solder layer formed on each terminal for a flip chip can fully be secured, without making solder adhere to the wire connection terminal closely formed to the terminal for a flip chip. As a result, improvement in the reliability of flip chip bonding can be aimed at.

摘要翻译： 在半导体器件的组装中，针对倒装芯片接合的可靠性的提高。 通过在封装衬底中用于倒装芯片的多个端子的端部的端部中形成虚拟端子，可以通过虚拟端子来抑制焊剂或焊料的流动，并且可以在多个端子上形成焊料层 的倒装芯片的端子。 由此，可以完全确保形成在倒装芯片的各个端子上的焊料层的厚度，而不会使焊料粘附到与倒装芯片的端子紧密形成的导线连接端子。 结果，可以针对倒装芯片接合的可靠性的提高。