公开(公告)号：US09558958B2

公开(公告)日：2017-01-31

申请号：US14494508

申请日：2014-09-23

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

IPC: H01L21/00 ,  H01L21/3105 ,  H01L21/78 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/31051 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49816 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

Abstract translation: 半导体晶片包含由锯条分隔开的多个半导体管芯。 在半导体晶片上形成绝缘层。 在绝缘层上形成保护层，该保护层包括沿着锯条的半导体管芯的边缘。 保护层覆盖半导体晶片的整个表面。 或者，在锯路上的保护层中形成开口。 绝缘层具有非平面表面，保护层具有平坦表面。 通过保护层和锯条将半导体晶片分离，以分离半导体管芯，同时保护半导体管芯的边缘。 与保护层一起，将半导体管芯安装到载体上。 密封剂沉积在半导体管芯和载体上。 去除载体和保护层。 在半导体管芯和密封剂上形成积层互连结构。

公开(公告)号：US09553162B2

公开(公告)日：2017-01-24

申请号：US13853969

申请日：2013-03-29

Applicant: STATS ChipPAC, Ltd.

Inventor： Thomas J. Strothmann ,  Steve Anderson ,  Byung Joon Han ,  Il Kwon Shim ,  Heap Hoe Kuan

IPC: H01L29/66 ,  H01L21/56 ,  H01L23/00 ,  H01L27/146 ,  H01L23/31

CPC classification number: H01L29/66 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/73209 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A conductive layer can be formed over the encapsulant and the semiconductor die. A transmissive layer can be formed over the semiconductor die. An interconnect structure can be formed through the encapsulant and electrically connected to the conductive layer, whereby the interconnect structure is formed off to only one side of the semiconductor die.

Abstract translation: 半导体器件具有沉积在半导体管芯上的半导体管芯和密封剂。 可以在密封剂和半导体管芯上方形成导电层。 可以在半导体管芯上形成透射层。 可以通过密封剂形成互连结构并且电连接到导电层，由此互连结构仅形成在半导体管芯的仅一侧。

公开(公告)号：US09548347B2

公开(公告)日：2017-01-17

申请号：US14289344

申请日：2014-05-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L28/10 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5228 ,  H01L23/528 ,  H01L24/73 ,  H01L28/40 ,  H01L2224/48463 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer.

Abstract translation: 半导体器件具有形成在聚合物基质复合衬底的第一表面上的第一绝缘层。 在第一绝缘层上形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 在第二绝缘层和第一导电层上形成第二导电层。 第二导电层被卷绕以表现出感应特性。 在第一导电层和第二导电层之间形成第三导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 在第二导电层上形成凸块。 可以在聚合物基质复合衬底的第二表面上形成第四绝缘层。 或者，可以在形成第一导电层之前，在第一绝缘层上形成第四绝缘层。

公开(公告)号：US09530738B2

公开(公告)日：2016-12-27

申请号：US14462347

申请日：2014-08-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Linda Pei Ee Chua ,  Byung Tai Do ,  Reza A. Pagaila

IPC: H01L23/48 ,  H01L23/02 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L21/56 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L25/03 ,  H01L25/00 ,  H01L23/552 ,  H01L21/768 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/288 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/17 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L29/40 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32502 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die.

公开(公告)号：US09484334B2

公开(公告)日：2016-11-01

申请号：US13716799

申请日：2012-12-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Robert C. Frye ,  Kai Liu

IPC: H03H7/42 ,  H01L27/01 ,  H01P5/10 ,  H03H7/48 ,  H01L21/70 ,  H05K1/02 ,  H03H5/00 ,  H05K1/16

CPC classification number: H01L27/01 ,  H01L21/70 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01P5/10 ,  H03H7/48 ,  H05K1/0233 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/025 ,  H05K1/165 ,  H05K2201/09245 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and RF coupler formed over the substrate. The RF coupler has a first conductive trace with a first end coupled to a first terminal of the semiconductor device, and a second conductive trace with a first end coupled to a second terminal of the semiconductor device. The first conductive trace is placed in proximity to a first portion of the second conductive trace. An integrated passive device is formed over the substrate. A second portion of the second conductive trace operates as a circuit component of the integrated passive device. The integrated passive device can be a balun or low-pass filter. The RF coupler also has a first capacitor coupled to the first terminal of the semiconductor device, and second capacitor coupled to a third terminal of the semiconductor device for higher directivity. The second conductive trace is wound to exhibit an inductive property.

公开(公告)号：US09478485B2

公开(公告)日：2016-10-25

申请号：US14261252

申请日：2014-04-24

Applicant: STATS ChipPAC, Ltd.

Inventor： XuSheng Bao ,  KwokKeung Szeto

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14134 ,  H01L2224/14135 ,  H01L2224/24147 ,  H01L2224/244 ,  H01L2224/821 ,  H01L2224/8236 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05572 ,  H01L2224/05664 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/13184 ,  H01L2924/00012

Abstract: A semiconductor device has a first semiconductor die. A first interconnect structure, such as a conductive pillar including a bump formed over the conductive pillar, and second interconnect structure are formed in a peripheral region of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die between the first interconnect structure and the second interconnect structure. A height of the second semiconductor die is less than a height of the first interconnect structure. A footprint of the second semiconductor die is smaller than a central region of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and second semiconductor die. Alternatively, the second semiconductor die is disposed over a semiconductor package including a plurality of interconnect structures. External connectivity from the single side fo-WLCSP is performed without the use of conductive vias to provide a high throughput and device reliability.

Abstract translation: 半导体器件具有第一半导体管芯。 在第一半导体管芯的周边区域中形成第一互连结构，例如包括形成在导电柱上的凸块的导电柱和第二互连结构。 第二半导体管芯设置在第一半导体管芯之间的第一互连结构和第二互连结构之间。 第二半导体管芯的高度小于第一互连结构的高度。 第二半导体管芯的占地面积小于第一半导体管芯的中心区域。 密封剂沉积在第一半导体管芯和第二半导体管芯上。 或者，第二半导体管芯设置在包括多个互连结构的半导体封装上。 执行单面fo-WLCSP的外部连接，而不使用导电通孔来提供高吞吐量和器件可靠性。

公开(公告)号：US09472452B2

公开(公告)日：2016-10-18

申请号：US14284752

申请日：2014-05-22

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L21/76879 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L2223/5448 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.

公开(公告)号：US09449925B2

公开(公告)日：2016-09-20

申请号：US13782939

申请日：2013-03-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

IPC: H01L29/00 ,  H01L23/538 ,  H01L23/00 ,  H01L27/12 ,  H01L49/02 ,  H01L21/683 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L23/5389 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L27/1266 ,  H01L28/00 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization.

Abstract translation: 半导体器件集成无源电路元件。 第一衬底形成在半导体器件的背面。 无源电路元件形成在绝缘层上。 无源电路元件可以是电感器，电容器或电阻器。 钝化层形成在无源电路元件上。 载体附着在钝化层上。 去除第一衬底。 在半导体器件的背面上的绝缘层上形成非硅衬底。 非硅衬底由玻璃，模塑料，环氧树脂，聚合物或聚合物复合材料制成。 在非硅衬底和绝缘层之间形成粘合剂层。 在绝缘层和第一钝化层之间形成通孔。 载体被移除。 在与无源电路元件电接触的钝化层之上形成凸起下金属化。 在凸块下方形成焊锡凸块。

公开(公告)号：US09443797B2

公开(公告)日：2016-09-13

申请号：US13832781

申请日：2013-03-15

Applicant: STATS ChipPAC, Ltd.

Inventor： Pandi C. Marimuthu ,  Sheila Marie L. Alvarez ,  Yaojian Lin ,  Jose A. Caparas ,  Yang Kern Jonathan Tan

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/2633 ,  H01L21/311 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/02311 ,  H01L2224/02379 ,  H01L2224/0558 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24227 ,  H01L2224/25171 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49174 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/821 ,  H01L2224/94 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

Abstract translation: 半导体器件具有设置在衬底的第一表面上的衬底和半导体管芯。 线柱附接到基底的第一表面。 线螺柱包括基部和杆部。 在衬底的第二表面上形成焊盘。 密封剂沉积在衬底，半导体管芯和线螺柱上。 密封剂的一部分被LDA去除以暴露线螺柱。 通过LDA去除一部分密封剂以暴露基底。 互连结构形成在密封剂上并电连接到线芯和半导体管芯。 在互连结构上形成凸点。 半导体封装设置在密封剂上并电连接到衬底。 分立半导体器件设置在密封剂上并电连接到衬底。

公开(公告)号：US09437538B2

公开(公告)日：2016-09-06

申请号：US14292925

申请日：2014-06-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

IPC: H01L23/538 ,  H01L23/522 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/552 ,  H01L23/498 ,  H01L25/03

CPC classification number: H01L23/522 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/30 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13157 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL.

Abstract translation: 半导体器件具有具有倾斜侧表面的第一半导体管芯。 第一半导体管芯安装到临时载体上。 RDL从第一半导体管芯的后表面沿着第一半导体管芯的倾斜侧表面延伸到载体。 密封剂沉积在载体上，RDL的一部分沿着倾斜的侧表面沉积。 第一半导体管芯的背面和RDL的一部分没有密封剂。 移除临时载体。 在第一半导体管芯的密封剂和暴露的有源表面上形成互连结构。 RDL电连接到互连结构。 第二半导体管芯安装在第一半导体管芯的后表面上。 第二半导体管芯具有与RDL电连接的突起。