公开(公告)号：US08535976B2

公开(公告)日：2013-09-17

申请号：US10454972

申请日：2003-06-04

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

IPC分类号： H01L21/44

CPC分类号： H01L24/82 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/82 ,  H01L2924/00

摘要： An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

摘要翻译： 集成芯片封装结构及其制造方法是通过将模具附着在陶瓷基板上并在模具和陶瓷基板的顶部上形成薄膜电路层。 其中薄膜电路层具有电连接到模具的金属焊盘的外部电路，其延伸到模具的有效表面外部的区域，以扇出模具的金属焊盘。 此外，多个有源器件和内部电路位于管芯的有效表面上。 有源器件的信号通过内部电路传输到外部电路，并通过内部电路从外部电路传输回其他有源器件。 此外，芯片封装结构允许将具有不同功能的多个裸片封装在集成封装中并通过外部电路电连接裸片。

公开(公告)号：US08421227B2

公开(公告)日：2013-04-16

申请号：US11769736

申请日：2007-06-28

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L23/5227 ,  H01L23/53238 ,  H01L23/53252 ,  H01L24/05 ,  H01L24/06 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05084 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2224/85201 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01032 ,  H01L2924/01031 ,  H01L2224/48869 ,  H01L2224/48744 ,  H01L2224/05552

摘要： A semiconductor chip structure includes a semiconductor substrate, an circuit structure, a passivation layer, a first adhesion/barrier layer, a metal cap and a metal layer. The semiconductor substrate has multiple electric devices located on a surface layer of a surface of the substrate. The circuit structure had multiple circuit layers electrically connecting with each other and electrically connecting with the electric devices. One of the circuit layers has multiple pads. The passivation layer is located on the circuit structure and has multiple openings penetrating through the passivation layer. The openings expose the pads. The first adhesion/barrier layer is over the pads and the passivation layer. The metal cap is located on the first adhesion/barrier layer and the passivation layer. The metal layer is on the metal layer.

摘要翻译： 半导体芯片结构包括半导体衬底，电路结构，钝化层，第一粘附/阻挡层，金属帽和金属层。 半导体衬底具有位于衬底表面的表面层上的多个电子器件。 电路结构具有彼此电连接并与电气装置电连接的多个电路层。 其中一个电路层具有多个焊盘。 钝化层位于电路结构上，具有贯穿钝化层的多个开口。 开口露出垫。 第一粘附/阻挡层在焊盘和钝化层之上。 金属盖位于第一粘附/阻挡层和钝化层上。 金属层在金属层上。

公开(公告)号：US08368204B2

公开(公告)日：2013-02-05

申请号：US13277142

申请日：2011-10-19

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

IPC分类号： H01L23/12 ,  H01L23/053 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76838 ,  H01L21/768 ,  H01L21/76807 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.

摘要翻译： 具有金属化结构的芯片和具有在金属化结构的第一和第二接触点上的第一和第二开口的绝缘层，连接第一和第二接触点的第一电路层，包括第一迹线部分，第一和第二通孔部分， 所述第一迹线部分和所述第一和第二接触点，所述第一电路层包括铜层和在所述铜层下面和所述第一迹线部分的侧壁处的第一导电层，以及第二电路层， 其第二通路部分在其底部，其中所述第二电路层包括另一铜层和位于所述另一铜层下方的第二导电层和所述第二迹线部分的侧壁处的第二导电层，以及第二电介质层， 第二电路层。

公开(公告)号：US08362588B2

公开(公告)日：2013-01-29

申请号：US13159147

申请日：2011-06-13

申请人： Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

发明人： Wen-Chieh Lee ,  Mou-Shiung Lin ,  Chien-Kang Chou ,  Yi-Cheng Liu ,  Chiu-Ming Chou ,  Jin-Yuan Lee

IPC分类号： H01L29/00 ,  H01L23/52 ,  H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/5227 ,  H01L23/525 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00

摘要： A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

公开(公告)号：US08350386B2

公开(公告)日：2013-01-08

申请号：US12691597

申请日：2010-01-21

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23/522

CPC分类号： H01L21/768 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/60 ,  H01L24/11 ,  H01L24/12 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist define electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

摘要翻译： 本发明在完成的半导体晶片的顶部上添加一层或多层厚的聚合物电介质和一层或多层厚的宽金属线，后钝化。 厚的宽金属线路可用于长信号路径，也可用于电源总线或电源平面，时钟分配网络，关键信号和用于倒装芯片应用的I / O焊盘的重新分配。 光刻胶定义电镀，溅射/蚀刻或双重和三重镶嵌技术用于形成金属线和通孔填充。

公开(公告)号：US20120193785A1

公开(公告)日：2012-08-02

申请号：US13358496

申请日：2012-01-25

申请人： Mou-Shiung Lin ,  Ping-Jung Yang ,  Hsin-Jung Lo ,  Te-Sheng Liu ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Ping-Jung Yang ,  Hsin-Jung Lo ,  Te-Sheng Liu ,  Jin-Yuan Lee

IPC分类号： H01L23/498

CPC分类号： H01L25/0657 ,  H01L21/76229 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05655 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48755 ,  H01L2224/48799 ,  H01L2224/48824 ,  H01L2224/48855 ,  H01L2224/80896 ,  H01L2224/8385 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12036 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1451 ,  H01L2924/14511 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/01046 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： Multichip packages or multichip modules may include stacked chips and through silicon/substrate vias (TSVs) formed using enclosure-first technology. Enclosure-first technology may include forming an isolation enclosure associated with a TSV early in the fabrication process, without actually forming the associated TSV. The TSV associated with the isolation enclosure is formed later in the fabrication process. The enclosure-first technology allows the isolation enclosures to be used as alignment marks for stacking additional chips. The stacked chips can be connected to each other or to an external circuit such that data input is provided through the bottom-most (or topmost) chip, data is output from the bottom-most (or topmost) chip. The multichip package may provide a serial data connection, and a parallel connection, to each of the stacked chips.

摘要翻译： 多芯片封装或多芯片模块可以包括堆叠芯片和通过使用封装第一技术形成的硅/衬底通孔（TSV）。 外壳首先技术可以包括在制造过程的早期形成与TSV相关联的隔离外壳，而不实际形成相关的TSV。 与隔离罩相关联的TSV在制造过程中稍后形成。 封装第一技术允许隔离外壳用作堆叠附加芯片的对准标记。 堆叠的芯片可以彼此连接或连接到外部电路，使得通过最底部（或最上面）芯片提供数据输入，数据从最底部（或最顶端）的芯片输出。 多芯片封装可以向每个堆叠的芯片提供串行数据连接和并联连接。

公开(公告)号：US08159070B2

公开(公告)日：2012-04-17

申请号：US12748295

申请日：2010-03-26

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23/48

CPC分类号： H01L23/53295 ,  H01L23/3114 ,  H01L23/5227 ,  H01L23/53223 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05082 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48669 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48869 ,  H01L2224/05552

摘要： Chip assemblies are disclosed that include a semiconductor substrate, multiple devices in and on the semiconductor substrate, a first metallization structure over the semiconductor substrate, and a passivation layer over the first metallization structure. First and second openings in the passivation layer expose first and second contact pads of the first metallization structure. A first metal post is positioned over the passivation layer and over the first contact pad. A second metal post is positioned over the passivation layer and over the second contact pad. A polymer layer is positioned over the passivation layer and encloses the first and second metal posts. A second metallization structure is positioned on the polymer layer, on the top surface of the first metal post and on the top surface of second metal post. The second metallization structure includes an electroplated metal. Related fabrication methods are also described.

摘要翻译： 公开了包括半导体衬底，半导体衬底中和半导体衬底上的多个器件，半导体衬底上的第一金属化结构以及第一金属化结构之上的钝化层的芯片组件。 钝化层中的第一和第二开口露出第一金属化结构的第一和第二接触焊盘。 第一金属柱位于钝化层上方并位于第一接触垫上。 第二金属柱位于钝化层上方并位于第二接触垫上。 聚合物层位于钝化层上方并包围第一和第二金属柱。 第二金属化结构位于聚合物层上，位于第一金属柱的顶表面和第二金属柱的顶表面上。 第二金属化结构包括电镀金属。 还描述了相关的制造方法。

公开(公告)号：US08026588B2

公开(公告)日：2011-09-27

申请号：US11707827

申请日：2007-02-16

申请人： Jin-Yuan Lee ,  Ying-Chih Chen ,  Mou-Shiung Lin

发明人： Jin-Yuan Lee ,  Ying-Chih Chen ,  Mou-Shiung Lin

IPC分类号： H01L21/60

CPC分类号： H01L24/48 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/854 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/04953 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

摘要翻译： 提供了一种方法和结构，以在集成电路管芯上形成的有源和/或无源器件和/或低k电介质上实现引线接合连接。 提供了具有有源和/或无源器件的半导体衬底，其中在有源和/或无源器件上形成互连金属化。 提供了形成在互连金属化之上的钝化层，其中在钝化层中形成开口以形成互连金属化的上金属层。 柔性金属焊盘形成在钝化层上方，其中柔性金属接合焊盘通过开口连接到上金属层，并且其中柔性金属接合焊盘基本上形成在有源和/或无源器件的上方。 顺应性金属接合焊盘可以由复合金属结构形成。

公开(公告)号：US08022546B2

公开(公告)日：2011-09-20

申请号：US12138453

申请日：2008-06-13

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23/522

CPC分类号： H01L21/768 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/60 ,  H01L24/11 ,  H01L24/12 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

公开(公告)号：US08004088B2

公开(公告)日：2011-08-23

申请号：US11854552

申请日：2007-09-13

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23/48

CPC分类号： H01L23/60 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/62 ,  H01L24/05 ,  H01L27/0248 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.