Patent search ap:("INVENSAS CORPORATION") AND inv:"Cyprian Emeka Uzoh" Page 16

151.

发明申请
Direct-Bonded LED Arrays and Applications 审中-公开

公开(公告)号：US20190088633A1

公开(公告)日：2019-03-21

申请号：US15919570

申请日：2018-03-13

Applicant: Invensas Corporation

Inventor： Min Tao , Liang Wang , Rajesh Katkar , Cyprian Emeka Uzoh

IPC: H01L25/16 , H01L25/075 , H01L33/62 , H01L33/32 , H01L33/38 , H01L27/12 , H01L33/60 , H01L33/58 , H01L33/00 , H01L33/44

Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

152.

发明授权
Via structure for signal equalization 有权

公开(公告)号：US10103093B2

公开(公告)日：2018-10-16

申请号：US15441783

申请日：2017-02-24

Applicant: Invensas Corporation

Inventor： Zhuowen Sun , Cyprian Emeka Uzoh , Yong Chen

IPC: H01L23/498 , H01L23/48 , H01L25/065 , H01L23/538 , H01L21/48 , H01L23/532 , H01L23/00

Abstract: An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure.

153.

发明授权
Low CTE component with wire bond interconnects 有权

公开(公告)号：US10032647B2

公开(公告)日：2018-07-24

申请号：US15587930

申请日：2017-05-05

Applicant: Invensas Corporation

Inventor： Rajesh Katkar , Cyprian Emeka Uzoh

IPC: H01L23/48 , H01L21/48 , H01L21/683 , H01L23/498

CPC classification number: H01L23/481 , H01L21/481 , H01L21/4853 , H01L21/486 , H01L21/4889 , H01L21/6835 , H01L21/76898 , H01L23/3731 , H01L23/3738 , H01L23/49827 , H01L24/43 , H01L24/46 , H01L2221/68345 , H01L2221/68359 , H01L2224/023 , H01L2224/4502 , H01L2924/00014 , H01L2924/15311 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.

154.

发明授权
Stacked die integrated circuit 有权

公开(公告)号：US09991231B2

公开(公告)日：2018-06-05

申请号：US15234425

申请日：2016-08-11

Applicant: Invensas Corporation

Inventor： Charles G. Woychik , Cyprian Emeka Uzoh , Ron Zhang , Daniel Buckminster , Guilian Gao

IPC: H01L21/48 , H01L25/065 , H01L21/52 , H01L21/78 , H01L23/48 , H01L23/498 , H01L23/00 , H01L21/768 , H01L21/304 , H01L21/56 , H01L23/31 , H01L25/00 , H01L23/13

CPC classification number: H01L25/0657 , H01L21/304 , H01L21/4853 , H01L21/486 , H01L21/52 , H01L21/565 , H01L21/76898 , H01L21/78 , H01L23/13 , H01L23/3114 , H01L23/481 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/85 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2224/13025 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/1703 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/92125 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06548 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589 , H01L2924/00014 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/16152 , H01L2924/16235 , H01L2924/16251 , H01L2924/181 , H01L2924/18161 , H01L2924/3511 , H01L2224/83 , H01L2224/81 , H01L2924/014 , H01L2924/0105 , H01L2924/00 , H01L2224/45099 , H01L2924/00012

Abstract: An apparatus relates generally to an integrated circuit package. In such an apparatus, a package substrate has a first plurality of via structures extending from a lower surface of the package substrate to an upper surface of the package substrate. An die has a second plurality of via structures extending to a lower surface of the die. The lower surface of the die faces the upper surface of the package substrate in the integrated circuit package. The package substrate does not include a redistribution layer. The die and the package substrate are coupled to one another.

155.

发明申请
Method and Apparatus for Stacking Devices in an Integrated Circuit Assembly 审中-公开

公开(公告)号：US20180130691A1

公开(公告)日：2018-05-10

申请号：US15629460

申请日：2017-06-21

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L21/683 , H01L21/67 , H01L23/00 , H01L25/00

CPC classification number: H01L21/6835 , H01L21/67092 , H01L21/67144 , H01L24/75 , H01L24/80 , H01L24/95 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68313 , H01L2221/68354 , H01L2221/68363 , H01L2224/08145 , H01L2224/7501 , H01L2224/753 , H01L2224/7565 , H01L2224/75755 , H01L2224/75804 , H01L2224/7598 , H01L2224/75983 , H01L2224/8001 , H01L2224/80896 , H01L2224/9511 , H01L2224/95136 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2924/00014 , H01L2224/80001

Abstract: Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both topside processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that topsides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks.

156.

发明申请
Tall and Fine Pitch Interconnects 审中-公开

公开(公告)号：US20180096960A1

公开(公告)日：2018-04-05

申请号：US15831231

申请日：2017-12-04

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh , Rajesh Katkar

IPC: H01L23/00 , H05K3/34 , H01L25/00 , H01L25/065 , H01L21/683

CPC classification number: H01L24/17 , H01L21/6835 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/034 , H01L2224/03612 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05644 , H01L2224/05655 , H01L2224/05666 , H01L2224/1012 , H01L2224/10155 , H01L2224/11003 , H01L2224/11013 , H01L2224/111 , H01L2224/1111 , H01L2224/1112 , H01L2224/1132 , H01L2224/11334 , H01L2224/114 , H01L2224/11438 , H01L2224/1144 , H01L2224/1147 , H01L2224/116 , H01L2224/1161 , H01L2224/11849 , H01L2224/119 , H01L2224/11912 , H01L2224/13014 , H01L2224/1308 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13171 , H01L2224/13181 , H01L2224/13184 , H01L2224/13187 , H01L2224/1329 , H01L2224/133 , H01L2224/13655 , H01L2224/13666 , H01L2224/13671 , H01L2224/13681 , H01L2224/13684 , H01L2224/1401 , H01L2224/1403 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81101 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81815 , H01L2224/92125 , H01L2225/06513 , H01L2924/01014 , H01L2924/01029 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/381 , H05K3/3436 , H05K3/3478 , H05K2203/0415 , H01L2924/00012 , H01L2924/00014 , H01L2924/00

Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

157.

发明授权
Methods and structures to repair device warpage 有权

公开(公告)号：US09859234B2

公开(公告)日：2018-01-02

申请号：US14819744

申请日：2015-08-06

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh , Guilian Gao , Bongsub Lee , Scott McGrath , Hong Shen , Charles G. Woychik , Arkalgud R. Sitaram , Akash Agrawal

IPC: H01L21/00 , H01L23/00 , H01L21/311 , H01L23/48 , H01L23/498 , H01L21/48 , H01L23/532

CPC classification number: H01L24/03 , H01L21/31144 , H01L21/486 , H01L23/291 , H01L23/293 , H01L23/3171 , H01L23/3192 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/53214 , H01L23/53228 , H01L23/53257 , H01L23/5329 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02126 , H01L2224/03009 , H01L2224/03464 , H01L2224/0401 , H01L2224/05025 , H01L2224/05144 , H01L2224/05155 , H01L2224/0557 , H01L2224/05571 , H01L2224/05572 , H01L2224/0558 , H01L2224/10126 , H01L2224/13016 , H01L2224/13022 , H01L2224/131 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/3511 , H01L2924/00012 , H01L2924/014

Abstract: A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.

158.

发明申请
METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS 审中-公开

公开(公告)号：US20170365546A1

公开(公告)日：2017-12-21

申请号：US15626687

申请日：2017-06-19

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh , Pezhman Monadgemi , Terrence Caskey , Fatima Lina Ayatollahi , Belgacem Haba , Charles G. Woychik , Michael Newman

IPC: H01L23/498 , H01L23/48 , H01L23/367 , H01L21/768 , H01L23/373 , H01L23/36

CPC classification number: H01L23/49827 , H01L21/76829 , H01L21/76898 , H01L23/36 , H01L23/367 , H01L23/3677 , H01L23/3736 , H01L23/481 , H01L23/49838 , H01L23/49866 , H01L2924/00 , H01L2924/0002

Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.