公开(公告)号：US06707682B2

公开(公告)日：2004-03-16

申请号：US09956909

申请日：2001-09-21

Applicant: Yutaka Akiba ,  Yasunori Narizuka ,  Hirayoshi Tanei ,  Naoya Kitamura

Inventor： Yutaka Akiba ,  Yasunori Narizuka ,  Hirayoshi Tanei ,  Naoya Kitamura

IPC: H05K118

CPC classification number: H05K1/0246 ,  H01L23/5383 ,  H01L23/552 ,  H01L25/16 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/092 ,  H05K1/113 ,  H05K1/115 ,  H05K1/162 ,  H05K1/167 ,  H05K3/403 ,  H05K3/4053 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/4652 ,  H05K3/467 ,  H05K9/0039 ,  H05K2201/0209 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09354 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/09663 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10045 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation of a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed.

Abstract translation: 通过将电源层的电位波动相对于在切换IC器件等而发生的接地层的电位波动转换为基底中的焦耳热而不使用任何部件作为对策来实现高安装密度的低EMI电路 针对EMI。 还公开了其结构，使用它的电路板以及制造电路板的方法。 从电源层和接地层观察的固体层之间的杂散电容的Q值的平行板线等效地减少，并且通过形成其中电阻器（电阻层）和另一接地层的结构匹配地终止 除了在多层电路板上的电源层和接地层之外提供。 还公开了封闭的屏蔽结构。

公开(公告)号：US20030030510A1

公开(公告)日：2003-02-13

申请号：US10192155

申请日：2002-07-11

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tomohiro Sasaki ,  Takahiro Azuma ,  Shigekatsu Yamamoto

IPC: H03H007/00

CPC classification number: H03H7/0115 ,  H03H2001/0085 ,  H05K1/0243 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09954 ,  H05K2201/10045 ,  Y02P70/613

Abstract: A multilayered LC composite component includes a main body having a pair of side surfaces, a pair of end surfaces, and an upper surface and a lower surface. Ground-side terminal electrodes are disposed at the center of the side surfaces and hot-side terminal electrodes are disposed along edges of the side surfaces. Each of the hot-side terminal electrodes includes an end surface extended portion extending to each of the end surfaces. The end-surface extended portion is arranged so that at least the approximate center of each of the end surfaces is exposed.

Abstract translation: 多层LC复合部件包括具有一对侧面，一对端面以及上表面和下表面的主体。 接地侧端子电极设置在侧面的中心，热侧端子电极沿着侧面的边缘设置。 每个热侧端子电极包括延伸到每个端面的端面延伸部分。 端面延伸部分被布置成使得至少每个端面的大致中心被露出。

公开(公告)号：US06278356B1

公开(公告)日：2001-08-21

申请号：US09572142

申请日：2000-05-17

Applicant: Wen-Yen Lin ,  Lin-Yeh Chen ,  Chin-Chi Chang ,  Shih-Ting Huang

Inventor： Wen-Yen Lin ,  Lin-Yeh Chen ,  Chin-Chi Chang ,  Shih-Ting Huang

IPC: H01L1012

CPC classification number: H05K1/167 ,  H05K1/095 ,  H05K1/162 ,  H05K3/064 ,  H05K2201/09763 ,  H05K2201/10045

Abstract: A flat, built-in resistor and capacitor has a substrate (10) made of dielectric material; a copper layer (12) formed on each surface of the substrate (10) and having an etched image (30) formed in each of the copper layers (12); a dielectric material layer (40) printed onto the copper layer (12) and filling up the etched image; and a resistance layer (50) printed onto the copper layer (12) and the dielectric material layer (40).

Abstract translation: 扁平的内置电阻器和电容器具有由电介质材料制成的衬底（10）; 形成在所述基板（10）的每个表面上并具有形成在每个所述铜层（12）中的蚀刻图像（30）的铜层（12）。 印刷在所述铜层（12）上并填充所述蚀刻图像的介电材料层（40）; 和印刷在铜层（12）和电介质材料层（40）上的电阻层（50）。

公开(公告)号：US4899126A

公开(公告)日：1990-02-06

申请号：US293416

申请日：1989-01-04

Applicant: Takeharu Yamada

Inventor： Takeharu Yamada

IPC: H01C1/14 ,  H01C7/00 ,  H01C13/02 ,  H01C17/24 ,  H01C17/28 ,  H01L27/01 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K3/28

CPC classification number: H01C17/281 ,  H05K1/167 ,  H05K3/28 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/095 ,  H05K2201/09236 ,  H05K2201/10045 ,  H05K2203/1453 ,  Y10T29/49101

Abstract: A thick film resistor type printed circuit board including an insulating substrate, a plurality of pairs of terminal electrode layers made of silver and formed on the insulating substrate, a plurality of resistor layers formed on the terminal electrode layers so as to connect the pairs of the terminal electrode layers, respectively, a plurality of wiring conductive layers made of copper and connected to predetermined ones of the terminal electrode layers so as to coat the predetermined ones of the terminal electrode layers and a protective layer for covering at least a portion of the insulating substrate, in which portion the terminal electrode layers and the resistor layers are formed.

Abstract translation: 一种厚膜电阻器型印刷电路板，包括绝缘基板，多个由银制成的端子电极层，形成在绝缘基板上，多个电阻层形成在端子电极层上，以便连接成对的 端子电极层，分别由铜制成并与预定的端子电极层连接的多个布线导电层，以覆盖预定的端子电极层和用于覆盖绝缘的至少一部分的保护层 衬底，其中形成端子电极层和电阻器层。

公开(公告)号：US4857002A

公开(公告)日：1989-08-15

申请号：US572173

申请日：1984-01-18

Applicant: William T. Jensen ,  Vincent B. Brown ,  Cathy J. Edgerton ,  Robert W. Masterson

Inventor： William T. Jensen ,  Vincent B. Brown ,  Cathy J. Edgerton ,  Robert W. Masterson

IPC: H01R12/58 ,  H01R12/70 ,  H05K1/09 ,  H05K1/14 ,  H05K1/16 ,  H05K3/34 ,  H05K3/42

CPC classification number: H01R12/7082 ,  H05K1/167 ,  H01R12/585 ,  H05K1/095 ,  H05K1/141 ,  H05K2201/10045 ,  H05K2201/10189 ,  H05K3/3447 ,  H05K3/42

Abstract: A compact terminator for interconnecting computer devices with each other and with peripheral equipment having contact ends to be interconnected with connectors. The contacts are interconnected on a circuit board employing thick film circuitry mounted thereon. The contacts are press fitted in plated through holes on the circuit board and form male or female connectors at one end. The device may be a differential or single ended type.

Abstract translation: 一种紧凑的终端器，用于将计算机设备彼此互连，并且具有外围设备，其具有与连接器互连的接触端。 触点在使用安装在其上的厚膜电路的电路板上互连。 触点压配在电路板的电镀通孔中，并在一端形成阳或阴连接器。 该器件可以是差分或单端型。

公开(公告)号：US20230380057A1

公开(公告)日：2023-11-23

申请号：US18318512

申请日：2023-05-16

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Taichi MISAWA ,  Keiji TANAKA

IPC: H05K1/02 ,  H05K3/10 ,  H05K3/12

CPC classification number: H05K1/0274 ,  H05K3/103 ,  H05K3/1258 ,  H05K2201/10045 ,  H05K2201/09981 ,  H05K2201/10121

Abstract: A package for an optical module includes a substrate provided through a side wall in a first direction. The substrate includes a first wiring layer including a first signal terminal, a second signal terminal, and a first ground terminal. The package includes a second wiring layer disposed under the first wiring layer. The second wiring layer includes a first ground pattern and a first insulating layer disposed between the first wiring layer and the second wiring layer, and includes a groove extending along the first direction, the groove being filled with a metal. The groove is provided within the first ground terminal, in a plan view, and the first insulating layer is free of the groove. The first ground terminal is electrically coupled to the first ground pattern through the metal of the groove.

公开(公告)号：US20230210023A1

公开(公告)日：2023-06-29

申请号：US17561439

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  JongSeok Park ,  Stefano Pellerano ,  Lester F. Lampert ,  Thomas F. Watson ,  Florian Luthi ,  James S. Clarke

IPC: H01L27/18 ,  H01L39/22 ,  H03H7/38 ,  H01P3/00 ,  H01L39/24 ,  H01L39/04 ,  G06N10/80 ,  H01L23/00 ,  H05K1/18

CPC classification number: H01L27/18 ,  H01L39/228 ,  H03H7/38 ,  H01P3/003 ,  H01L39/24 ,  H01L39/04 ,  H01L39/221 ,  G06N10/80 ,  H01L24/48 ,  H01L24/45 ,  H01L2224/49171 ,  H01L2224/45144 ,  H05K2201/10045 ,  H01L2924/0495 ,  H01L2224/48225 ,  H01L2224/45186 ,  H05K2201/10522 ,  H05K1/18 ,  H01L2224/45147 ,  H01L2224/48153

Abstract: Technologies for radiofrequency optimized interconnects for a quantum processor are disclosed. In the illustrative embodiment, signals are carried in coplanar waveguides on a surface of a quantum processor die. A ground ring surrounds the signals and is connected to the ground conductors of each coplanar waveguide. Wire bonds connect the ground ring to a ground of a circuit board. The wire bonds provide both an electrical connection from the quantum processor die to the circuit board as well as increased thermal coupling between the quantum processor die and the circuit board, increasing cooling of the quantum processor die.

公开(公告)号：US20170250029A1

公开(公告)日：2017-08-31

申请号：US15597105

申请日：2017-05-16

Applicant: ROHM CO., LTD.

Inventor： Hiroki YAMAMOTO ,  Keishi WATANABE ,  Hiroshi TAMAGAWA

IPC: H01G7/06 ,  H01G4/40 ,  H01G2/06

CPC classification number: H01G4/30 ,  H01G2/06 ,  H01G4/005 ,  H01G4/228 ,  H01G4/232 ,  H01G4/40 ,  H01L22/14 ,  H01L22/20 ,  H01L23/5223 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0676 ,  H01L27/101 ,  H01L27/2409 ,  H01L28/40 ,  H01L29/66189 ,  H01L29/94 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/0002 ,  H05K1/111 ,  H05K1/162 ,  H05K1/18 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/10045 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

公开(公告)号：US09633779B2

公开(公告)日：2017-04-25

申请号：US14456674

申请日：2014-08-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Young Ghyu Ahn ,  Byoung Hwa Lee ,  Sang Soo Park ,  Min Cheol Park

IPC: H01G4/30 ,  H01G4/005 ,  H01G4/228 ,  H01F29/00 ,  H03H7/01 ,  H01G4/01 ,  H05K1/11 ,  H01G4/40 ,  H01G4/012 ,  H01G4/232 ,  H01F27/28 ,  H01F27/29 ,  H01F27/40 ,  H01G2/20 ,  H01G4/06 ,  H03H7/00 ,  H01G4/12

CPC classification number: H01F29/00 ,  H01F27/2804 ,  H01F27/292 ,  H01F27/40 ,  H01F2027/2809 ,  H01G4/005 ,  H01G4/01 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1209 ,  H01G4/228 ,  H01G4/232 ,  H01G4/30 ,  H01G4/40 ,  H03H7/0115 ,  H05K1/111 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10045 ,  Y02P70/611

Abstract: A composite electronic component may include: a composite body including a capacitor and an inductor coupled to each other, the capacitor having a ceramic body in which dielectric layers and internal electrodes facing each other with the dielectric layers interposed therebetween are stacked, and the inductor having a magnetic body in which magnetic layers having conductive patterns are stacked; an input terminal disposed on a first end surface of the composite body; an output terminal including a first output terminal disposed on a second end surface of the composite body and a second output terminal disposed on any one or more of upper and lower surfaces and a second side surface of the capacitor; and a ground terminal disposed on any one or more of the upper and lower surfaces and a first side surface of the capacitor and connected to the internal electrodes.

公开(公告)号：US20150043185A1

公开(公告)日：2015-02-12

申请号：US14456674

申请日：2014-08-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Young Ghyu AHN ,  Byoung Hwa LEE ,  Sang Soo PARK ,  Min Cheol PARK

IPC: H01G17/00 ,  H01G4/12 ,  H05K1/18 ,  H01F27/29 ,  H01F27/24 ,  H01F29/00 ,  H01G4/30 ,  H01G4/228

CPC classification number: H01F29/00 ,  H01F27/2804 ,  H01F27/292 ,  H01F27/40 ,  H01F2027/2809 ,  H01G4/005 ,  H01G4/01 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1209 ,  H01G4/228 ,  H01G4/232 ,  H01G4/30 ,  H01G4/40 ,  H03H7/0115 ,  H05K1/111 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10045 ,  Y02P70/611

Abstract: A composite electronic component may include: a composite body including a capacitor and an inductor coupled to each other, the capacitor having a ceramic body in which dielectric layers and internal electrodes facing each other with the dielectric layers interposed therebetween are stacked, and the inductor having a magnetic body in which magnetic layers having conductive patterns are stacked; an input terminal disposed on a first end surface of the composite body; an output terminal including a first output terminal disposed on a second end surface of the composite body and a second output terminal disposed on any one or more of upper and lower surfaces and a second side surface of the capacitor; and a ground terminal disposed on any one or more of the upper and lower surfaces and a first side surface of the capacitor and connected to the internal electrodes.

Abstract translation: 复合电子部件可以包括：复合体，其包括彼此耦合的电容器和电感器，所述电容器具有陶瓷体，所述陶瓷体叠置有介电层和彼此面对的电介质层的内部电极，所述电感器具有 堆叠具有导电图案的磁性层的磁性体; 输入端子，设置在复合体的第一端面上; 输出端子，包括设置在复合体的第二端面上的第一输出端子和设置在电容器的上表面和下表面中的任一个或多个上的第二输出端子和第二侧表面; 以及设置在所述上​​表面和所述下表面中的任一个或多个上的接地端子和所述电容器的第一侧表面并连接到所述内部电极。