公开(公告)号：US20140140030A1

公开(公告)日：2014-05-22

申请号：US14163031

申请日：2014-01-24

申请人： FUJITSU LIMITED

发明人： Seiki Sakuyama ,  Taiji Sakai

IPC分类号： H05K1/11

CPC分类号： H05K1/115 ,  H01B1/026 ,  H01B1/22 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K3/462 ,  H05K2201/0218 ,  H05K2201/0272 ,  H05K2201/10378 ,  H05K2203/0425 ,  H01L2224/0401

摘要： A conductive material includes a first metal part whose main ingredient is a first metal; a second metal part formed on the first metal part and whose main ingredient is a second metal, the second metal having a melting point lower than a melting point of the first metal, which second metal can form a metallic compound with the first metal; and a third metal part whose main ingredient is a third metal, which third metal can make a eutectic reaction with the second metal.

摘要翻译： 导电材料包括主要成分是第一金属的第一金属部分; 第二金属部分形成在第一金属部分上，其主要成分是第二金属，第二金属的熔点低于第一金属的熔点，第二金属可以与第一金属形成金属化合物; 和主要成分为第三金属的第三金属部分，该第三金属可以与第二金属发生共晶反应。

公开(公告)号：US20140090767A1

公开(公告)日：2014-04-03

申请号：US14099207

申请日：2013-12-06

申请人： Rogers Corporation

发明人： Sankar Paul ,  Scott D. Kennedy ,  Dirk M. Baars

IPC分类号： H05K3/00

CPC分类号： H05K3/4626 ,  B32B3/04 ,  B32B3/08 ,  B32B3/18 ,  B32B3/30 ,  B32B5/08 ,  B32B5/16 ,  B32B5/30 ,  B32B7/12 ,  B32B15/06 ,  B32B15/08 ,  B32B15/14 ,  B32B15/16 ,  B32B15/20 ,  B32B25/08 ,  B32B25/14 ,  B32B27/08 ,  B32B27/12 ,  B32B27/14 ,  B32B27/20 ,  B32B27/26 ,  B32B27/285 ,  B32B27/302 ,  B32B27/32 ,  B32B27/38 ,  B32B2255/10 ,  B32B2255/205 ,  B32B2260/025 ,  B32B2260/046 ,  B32B2262/0269 ,  B32B2262/101 ,  B32B2262/14 ,  B32B2264/10 ,  B32B2264/102 ,  B32B2264/104 ,  B32B2264/12 ,  B32B2270/00 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/30 ,  B32B2307/302 ,  B32B2307/3065 ,  B32B2307/308 ,  B32B2307/7265 ,  B32B2457/00 ,  B32B2457/08 ,  C08G65/485 ,  C08K3/013 ,  C08L9/00 ,  C08L13/00 ,  C08L15/00 ,  C08L19/006 ,  C08L51/04 ,  C08L71/12 ,  C08L71/126 ,  C08L2666/08 ,  C08L2666/14 ,  C09J107/00 ,  C09J113/00 ,  C09J171/12 ,  H05K1/0393 ,  H05K3/00 ,  H05K3/462 ,  H05K3/4641 ,  H05K3/4676 ,  H05K2201/0133 ,  H05K2201/0158 ,  H05K2201/0355 ,  H05K2201/10378 ,  Y10T156/10 ,  Y10T428/24802 ,  Y10T428/263 ,  Y10T428/31544 ,  Y10T428/31931 ,  C08L2666/04

摘要： A circuit subassembly, comprising a dielectric layer formed from a dielectric composition comprising, based on the total volume of the composition: about 15 to about 65 volume percent of a dielectric filler; and about 35 to about 85 volume percent of a thermosetting composition comprising: a poly(arylene ether), and a carboxy-functionalized polybutadiene or polyisoprene polymer.

摘要翻译： 一种电路子组件，包括由电介质组合物形成的电介质层，所述电介质层包含基于所述组合物的总体积：约15至约65体积％的介电填料; 和约35至约85体积％的热固性组合物，其包含：聚（亚芳基醚）和羧基官能化聚丁二烯或聚异戊二烯聚合物。

公开(公告)号：US08476534B2

公开(公告)日：2013-07-02

申请号：US12810522

申请日：2008-12-19

申请人： Satoru Zama ,  Kenichi Ohga ,  Akira Tachibana

发明人： Satoru Zama ,  Kenichi Ohga ,  Akira Tachibana

IPC分类号： H05K1/14 ,  H05K1/09 ,  B32B37/00

CPC分类号： H05K3/4614 ,  H05K3/281 ,  H05K3/426 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/035 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/063 ,  Y10T156/10

摘要： Provided is a multilayer printed board 10 having three single-sided conductor pattern films 16 each having a conductor pattern 13 formed on one surface of a resin film 12 having a through hole 11 and a filled through hole 15 that is the through hole 11 filled with a conductor 14 integrally with the conductor pattern 13. These single-sided conductor pattern films 16 are stacked in such a manner that their tops are oriented in the same way. The conductor patterns 13 of the single-sided conductor pattern films 16 are electrically connected via the filled through holes 15. As the conductor patterns 13 of the single-sided conductor pattern films 16 are interlayer connected via the filled through holes 15, the interlayer connection reliability can be enhanced.

摘要翻译： 提供了具有三个单面导体图案膜16的多层印刷电路板10，每个单面导体图案膜16具有形成在具有通孔11的树脂膜12的一个表面上的导体图案13和填充有通孔11的填充通孔15， 与导体图案13一体地形成的导体14.这些单面导体图案膜16以它们的顶部以相同的方式定向的方式堆叠。 单面导体图案膜16的导体图案13经由填充的通孔15电连接。当单面导体图案膜16的导体图案13经由填充的通孔15层间连接时，层间连接 可靠性可以提高。

公开(公告)号：US08453322B2

公开(公告)日：2013-06-04

申请号：US12539172

申请日：2009-08-11

申请人： Raj Kumar ,  Monte Dreyer ,  Michael J. Taylor ,  Ruben Zepeda

发明人： Raj Kumar ,  Monte Dreyer ,  Michael J. Taylor ,  Ruben Zepeda

IPC分类号： H01K3/10

CPC分类号： H05K3/4614 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/427 ,  H05K3/429 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2203/0191 ,  H05K2203/0554 ,  H05K2203/061 ,  H05K2203/1152 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49165

摘要： Methods of manufacturing at least a portion of a printed circuit board. The circuit board is formed to include a plurality of sub-assemblies, each of the sub-assemblies including a plurality of circuit layers and having at least one countersink and at least one hole, the countersink having a first diameter and a first depth from a first side of at least one of the sub-assemblies and into the at least one sub-assembly, the hole having a second diameter smaller than the first diameter and a second depth longer than the first depth from the first side of the at least one sub-assembly and into the at least one sub-assembly at the countersink; a metal metalized within the hole and the countersink; a lamination adhesive interposed between one and a corresponding one of the sub-assemblies and having at least one via formed therethrough; and a counter paste filled within the via.

摘要翻译： 制造印刷电路板的至少一部分的方法。 电路板形成为包括多个子组件，每个子组件包括多个电路层并且具有至少一个埋头孔和至少一个孔，该埋头孔具有第一直径和从第一深度 至少一个子组件的第一侧并且进入至少一个子组件，该孔具有小于第一直径的第二直径和比该至少一个子组件的第一侧的第一深度长的第二深度 子组件并进入至少一个子组件在锪孔处; 孔内金属化和埋头孔; 插入在一个和相应的一个子组件之间并且具有通过其形成的至少一个通孔的层压粘合剂; 以及填充在通孔内的计数器糊状物。

公开(公告)号：US20120280022A1

公开(公告)日：2012-11-08

申请号：US13551586

申请日：2012-07-17

申请人： Tzu-Wei Huang

发明人： Tzu-Wei Huang

IPC分类号： H05K3/00 ,  B23K15/00

CPC分类号： H05K3/4682 ,  B23K11/11 ,  B23K2101/42 ,  B32B37/0084 ,  B32B37/02 ,  B32B37/04 ,  B32B38/04 ,  B32B38/10 ,  B32B2038/047 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2311/00 ,  B32B2311/12 ,  B32B2457/00 ,  B32B2457/08 ,  H05K1/115 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/02 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/46 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/09918 ,  H05K2203/1536 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.

摘要翻译： 电路基板的制造方法包括以下步骤。 两个金属层的周边结合形成密封区域。 在两个金属层上形成两个绝缘层。 在两个绝缘层上形成包括上，下导电层的两个。 然后，将两个绝缘层和两个导电层层压，使得彼此接合的两个金属层嵌入在两个绝缘层之间。 去除两个绝缘层的一部分和两个导电层的一部分以形成暴露两个金属层的多个盲孔。 在盲孔和剩余的两个导电层上形成导电材料。 两个金属层的密封区域被分离以形成两个分开的电路基板。

公开(公告)号：US20120228007A1

公开(公告)日：2012-09-13

申请号：US13473542

申请日：2012-05-16

申请人： Young Gwan KO

发明人： Young Gwan KO

IPC分类号： H05K1/02

CPC分类号： H05K3/462 ,  H05K3/007 ,  H05K3/107 ,  H05K3/28 ,  H05K3/4602 ,  H05K2201/09536 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

摘要： Disclosed are a printed circuit board including a core substrate including core circuit layers on both sides thereof, a first build-up layer formed on one side of the core substrate, a second build-up layer formed on the other side of the core substrate, and first and second protective layers formed on the first and second build-up layers, respectively, wherein the first build-up layer includes a trench circuit layer as an outermost circuit layer formed by a trench technology, the trench circuit layer is embedded in the first protective layer, and an outermost circuit layer of the second build-up layer is embedded in an outermost insulating layer of the second build-up layer, and a method of manufacturing the printed circuit board. Thanks to the formation of the outermost circuit layer by the trench technology, it is difficult to separate the outermost circuit layer from the outermost insulating layer.

摘要翻译： 公开了一种印刷电路板，其包括其两侧具有芯电路层的芯基板，形成在芯基板的一侧上的第一累积层，形成在芯基板的另一侧上的第二累积层， 以及分别形成在第一和第二堆积层上的第一和第二保护层，其中第一堆积层包括作为通过沟槽技术形成的最外层电路层的沟槽电路层，沟槽电路层嵌入 第一保护层和第二堆积层的最外层电路层嵌入第二堆积层的最外绝缘层中，以及制造印刷电路板的方法。 由于通过沟槽技术形成最外层电路层，难以将最外层电路层与最外层绝缘层分开。

公开(公告)号：US20120152605A1

公开(公告)日：2012-06-21

申请号：US12972700

申请日：2010-12-20

申请人： Rabindra N. Das ,  John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, JR.

发明人： Rabindra N. Das ,  John M. Lauffer ,  Voya R. Markovich ,  James J. McNamara, JR.

IPC分类号： H05K1/11 ,  H05K3/36

CPC分类号： H05K3/462 ,  H05K1/162 ,  H05K1/167 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2203/063 ,  Y10T29/49099 ,  Y10T29/49126 ,  Y10T29/49165

摘要： A circuitized substrate and method of making same in which quantities of thru-holes are formed within a dielectric interposer layer. The substrate includes two printed circuit board (PCB) layers bonded to opposing sides of the interposer with electrically conductive features of each PCB aligned with the interposer thru-holes. Resistive paste is positioned on the conductive features located adjacent the thru-holes to form controlled electrically resistive connections between conductive features of the two PCBs. A circuitized substrate assembly and method of making same are also disclosed.

摘要翻译： 电路基板及其制造方法，其中在电介质中介层内形成有通孔数量。 基板包括两个印刷电路板（PCB）层，其结合到插入件的相对侧，每个PCB的导电特征与插入件通孔对准。 电阻浆料位于邻近通孔的导电特征上，以在两个PCB的导电特征之间形成受控的电阻连接。 还公开了电路化基板组件及其制造方法。

公开(公告)号：US08198541B2

公开(公告)日：2012-06-12

申请号：US12519745

申请日：2007-12-14

申请人： Kenji Sasaoka ,  Yoshitaka Fukuoka

发明人： Kenji Sasaoka ,  Yoshitaka Fukuoka

IPC分类号： H05K7/20 ,  H01K1/00

CPC分类号： H05K1/0206 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/186 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4647 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2203/061 ,  H05K2203/063 ,  Y10T29/49002 ,  H01L2224/0401

摘要： An electronic component built-in wiring board includes: at least a pair of wiring patterns; an insulating layer disposed between the pair of wiring board; an electronic component embedded in the insulating layer; and a metallic body provided at least on or above a main surface of the electronic component in the insulating layer and thermally contacted with the electronic component.

摘要翻译： 电子部件内置布线板包括：至少一对布线图案; 绝缘层，设置在所述一对布线板之间; 嵌入绝缘层中的电子部件; 以及金属体，其设置在所述绝缘层中至少在所述电子部件的主表面上或上方，并与所述电子部件热接触。

公开(公告)号：US08154114B2

公开(公告)日：2012-04-10

申请号：US11834395

申请日：2007-08-06

申请人： Reinhold Bayerer

发明人： Reinhold Bayerer

IPC分类号： H01L23/12

CPC分类号： H01L23/3735 ,  C04B37/021 ,  C04B37/026 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/402 ,  C04B2237/407 ,  H01L23/3731 ,  H01L23/3736 ,  H01L24/28 ,  H01L24/29 ,  H01L24/34 ,  H01L24/37 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/072 ,  H01L25/165 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/371 ,  H01L2224/37599 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48699 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0306 ,  H05K1/053 ,  H05K3/4061 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4629 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09554 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/83205 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A power semiconductor module is disclosed. One embodiment includes a multilayer substrate having a plurality of metal layers and a plurality of ceramic layers, where the ceramic layers are located between the metal layers.

摘要翻译： 公开了功率半导体模块。 一个实施例包括具有多个金属层和多个陶瓷层的多层基板，其中陶瓷层位于金属层之间。

公开(公告)号：US08058558B2

公开(公告)日：2011-11-15

申请号：US11984115

申请日：2007-11-13

申请人： Jee-Soo Mok ,  Dong-Jin Park ,  Jun-Heyoung Park ,  Ki-Hwan Kim ,  Sung-Young Kim

发明人： Jee-Soo Mok ,  Dong-Jin Park ,  Jun-Heyoung Park ,  Ki-Hwan Kim ,  Sung-Young Kim

IPC分类号： H05K1/00 ,  H05K7/06

CPC分类号： H05K3/462 ,  H05K3/4069 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2203/0554 ,  Y10T29/49155

摘要： A printed circuit board and a manufacturing method thereof are disclosed. Using a method of manufacturing a printed circuit board which includes forming a circuit pattern, which includes lands, on a first board; forming a paste bump on the land of the first board; and stacking an insulation on a surface of the first board such that the paste bump penetrates the insulation, where the paste bump is formed to cover the land of the first board, the areas of the lands can be reduced to manufacture a printed circuit board of high density, and the contact reliability can be increased due to the increase in contact area between the lands and paste bumps to improve the performance of the high-density printed circuit-board.

摘要翻译： 公开了印刷电路板及其制造方法。 使用制造印刷电路板的方法，其包括在第一板上形成包括焊盘的电路图案; 在第一板的焊盘上形成焊膏; 并且在所述第一板的表面上堆叠绝缘体，使得所述焊膏凸块穿过形成所述焊膏以覆盖所述第一板的焊盘的所述绝缘体，所述焊盘的区域可以被减小以制造印刷电路板 高密度，并且由于焊盘和焊膏之间的接触面积的增加可以提高接触可靠性，以提高高密度印刷电路板的性能。