公开(公告)号：US20050189136A1

公开(公告)日：2005-09-01

申请号：US11106642

申请日：2005-04-15

Applicant: Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

Inventor： Yogo Kawasaki ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/34 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/382 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0796 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Through holes 36 are formed to penetrate a core substrate 30 and lower interlayer resin insulating layers 50, and via holes 66 are formed right on the through holes 36, respectively. Due to this, the through holes 36 and the via holes 66 are arranged linearly, thereby making it possible to shorten wiring length and to accelerate signal transmission speed. Also, since the through holes 36 and the via holes 66 to be connected to solder bumps 76 (conductive connection pins 78), respectively, are directly connected to one another, excellent reliability in connection is ensured.

Abstract translation: 通孔36形成为穿透芯基板30和下层层间树脂绝缘层50，并且通孔66分别形成在通孔36上。 由此，通孔36和通路孔66线性配置，能够缩短布线长度，加速信号传输速度。 此外，由于分别连接到焊料凸块76（导电连接销78）的通孔36和通孔66彼此直接连接，所以确保了良好的连接可靠性。

公开(公告)号：US06931724B2

公开(公告)日：2005-08-23

申请号：US10207259

申请日：2002-07-30

Applicant: Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

Inventor： Akio Rokugawa ,  Masayuki Sasaki ,  Yuichi Matsuda

IPC: H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/20 ,  H05K3/38 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/4682 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/113 ,  H05K3/007 ,  H05K3/045 ,  H05K3/108 ,  H05K3/20 ,  H05K3/205 ,  H05K3/388 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/0384 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49345

Abstract: A method of producing a multilayered substrate having: a first face being provided with pads bondable to electrode terminals of a semiconductor element, and a body containing a plurality of wiring line layers and insulation layers successively formed from the side of the multilayered substrate at which the face for mounting a semiconductor element is located, wherein the final insulating layer forms provides a second face of the multilayered substrate. The successive wiring line layers are connected by vias, and the second face has external connection terminal pads. The pads on the first face are formed on a metal sheet, a first layer of insulating material is formed on the metal sheet so as to cover the pads formed thereon, holes are formed through the insulating material to expose the end face of the pad, and a patterned metal layer is formed to provide a layer of wiring lines and vias connecting the pads with the wiring line on the layer of insulating material. Subsequently, layers of insulation material are formed to cover the layers of wiring lines, where vias are formed in the insulating material layers, and then patterned metal wiring line layers and filled vias are formed, until the predetermined number of sets of an insulation layer and a wiring line layer is obtained. The metal sheet is then removed.

Abstract translation: 一种多层基板的制造方法，其特征在于，具有：第一面，其具有可与半导体元件的电极端子连接的焊盘;以及主体，其包含从所述多层基板的一侧依次形成的多个布线层和绝缘层， 定位用于安装半导体元件的面，其中最终绝缘层形成提供多层基底的第二面。 连续的布线层通过通孔连接，第二面具有外部连接端子焊盘。 第一面上的焊盘形成在金属板上，在金属板上形成第一绝缘材料层，以覆盖形成在其上的焊盘，通过绝缘材料形成孔，露出焊盘的端面， 并且形成图案化金属层以提供将焊盘与绝缘材料层上的布线连接的布线线和通孔层。 随后，形成绝缘材料层以覆盖在绝缘材料层中形成通孔的布线层，然后形成图案化的金属布线层和填充的通孔，直到预定数量的绝缘层和 得到布线层。 然后去除金属片。

公开(公告)号：US20050157478A1

公开(公告)日：2005-07-21

申请号：US11062672

申请日：2005-02-23

Applicant: Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/64 ,  H01L25/16 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46 ,  H01L23/52

CPC classification number: H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract translation: 片状电容器20设置在印刷电路板10中。以这种方式，IC芯片90和每个片状电容器20之间的距离缩短，并且环路电感减小。 此外，芯片电容器20被容纳在具有大厚​​度的芯基板30中。 因此，印刷电路板的厚度不会变大。

公开(公告)号：US20050152097A1

公开(公告)日：2005-07-14

申请号：US11031764

申请日：2005-01-07

Applicant: Hideaki Sakaguchi ,  Mitsutoshi Higashi ,  Takashi Mochizuki

Inventor： Hideaki Sakaguchi ,  Mitsutoshi Higashi ,  Takashi Mochizuki

IPC: H01G9/028 ,  H01G9/00 ,  H01G9/02 ,  H05K1/16 ,  H05K3/46

CPC classification number: H01G9/028 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09509 ,  Y10T29/417

Abstract: In a capacitor 10, a first electrode 21, a dielectric layer 23, a solid electrolytic layer 50 and a second electrode 31 are provided. In a manufacturing process, the dielectric layer 23 and a first solid electrolytic layer 24 formed by a chemical polymerization film are provided on the first electrode 21 side, while a second solid electrolytic layer 32 formed by an electrolytic polymerization film is provided on the second electrode 31 side. Then, the solid electrolytic layers are bonded to each other.

Abstract translation: 在电容器10中，设置有第一电极21，电介质层23，固体电解质层50和第二电极31。 在制造工序中，在第一电极21侧设置电介质层23和由化学聚合膜形成的第一固体电解质层24，在第二电极上设置由电解聚合膜形成的第二固体电解质层32 31边。 然后，固体电解质层彼此结合。

公开(公告)号：US06916685B2

公开(公告)日：2005-07-12

申请号：US10686435

申请日：2003-10-14

Applicant: Wei-Sheng Yang ,  Chih-Liang Chu ,  Kuo-Sheng Wei

Inventor： Wei-Sheng Yang ,  Chih-Liang Chu ,  Kuo-Sheng Wei

IPC: H01L21/48 ,  H05K3/24 ,  H01L21/44

CPC classification number: H05K3/242 ,  H01L21/4846 ,  H01L2924/0002 ,  H05K3/243 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2203/0542 ,  H05K2203/1581 ,  H01L2924/00

Abstract: A method of plating a metal layer over isolated pads on a semiconductor package substrate is proposed. This substrate is formed with a plurality of conductive blind vias. The isolated pads are formed on a surface of the substrate, each having a plating line extending towards one blind via but electrically insulated from the blind via by an electrically insulating region. A conductive film covers the surface of the substrate having the isolated pads, and a photoresist layer is formed over the conductive film. The photoresist layer has openings for exposing a portion of the conductive film covering the isolated pads. The exposed portion of the conductive film is removed, to allow a metal layer to be plated on the isolated pads. Then, the photoresist layer and the remainder of the conductive film are removed, and the electrical insulation between the isolated pads and the blind vias is restored.

Abstract translation: 提出了在半导体封装基板上的隔离焊盘上镀覆金属层的方法。 该衬底形成有多个导电盲孔。 孤立的焊盘形成在衬底的表面上，每个衬底具有朝向一个盲孔通过的电镀线，但是通过电绝缘区与盲孔电绝缘。 导电膜覆盖具有隔离焊盘的衬底的表面，并且在导电膜上形成光致抗蚀剂层。 光致抗蚀剂层具有用于暴露覆盖隔离垫的导电膜的一部分的开口。 去除导电膜的暴露部分，以允许将金属层电镀在隔离的焊盘上。 然后，去除光致抗蚀剂层和导电膜的其余部分，并且恢复隔离焊盘和盲孔之间的电绝缘。

公开(公告)号：US20050128720A1

公开(公告)日：2005-06-16

申请号：US10736327

申请日：2003-12-15

Applicant: Robert Croswell ,  Gregory Dunn ,  Robert Lempkowski ,  Aroon Tungare ,  Jovica Savic

Inventor： Robert Croswell ,  Gregory Dunn ,  Robert Lempkowski ,  Aroon Tungare ,  Jovica Savic

IPC: H01G20060101 ,  H05K1/16 ,  H05K3/00 ,  H05K3/02 ,  H05K3/42 ,  H05K3/46 ,  H05K7/06

CPC classification number: H05K1/162 ,  H05K3/0029 ,  H05K3/025 ,  H05K3/384 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: One of a plurality of capacitors embedded in a printed circuit structure includes a first electrode (415) overlaying a first substrate layer (505) of the printed circuit structure, a crystallized dielectric oxide core (405) overlaying the first electrode, a second electrode (615) overlying the crystallized dielectric oxide core, and a high temperature anti-oxidant layer (220) disposed between and contacting the crystallized dielectric oxide core and at least one of the first and second electrodes. The crystallized dielectric oxide core has a thickness that is less than 1 micron and has a capacitance density greater than 1000 pF/mm2. The material and thickness are the same for each of the plurality of capacitors. The crystallized dielectric oxide core may be isolated from crystallized dielectric oxide cores of all other capacitors of the plurality of capacitors.

Abstract translation: 嵌入印刷电路结构中的多个电容器之一包括覆盖印刷电路结构的第一衬底层（505）的第一电极（415），覆盖第一电极的结晶化电介质氧化物芯（405），第二电极 615），以及设置在结晶的电介质氧化物芯和第一和第二电极中的至少一个之间并与其接触的高温抗氧化剂层（220）。 结晶的电介质氧化物芯的厚度小于1微米，电容密度大于1000pF / mm 2。 多个电容器的材料和厚度相同。 结晶的电介质氧化物芯可以与多个电容器的所有其它电容器的结晶的电介质氧化物芯隔离。

公开(公告)号：US06896173B2

公开(公告)日：2005-05-24

申请号：US10710561

申请日：2004-07-21

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: B23K1/00 ,  B23K1/19 ,  B23K1/20 ,  H01L21/48 ,  H05K3/24 ,  H05K3/28 ,  B23K31/02

CPC classification number: H01L21/4857 ,  B23K1/0018 ,  B23K1/19 ,  B23K1/20 ,  B23K2101/42 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09881 ,  H05K2203/054 ,  H05K2203/0542

Abstract: The present invention provides a method of fabricating a circuit substrate. First, a substrate having first pads and second pads is provided, wherein the first pads and second pads are arranged respectively on a first surface and a second surface of the substrate. The first pads are electrically connected to the second pads. Next, a conductive seed layer is formed on the second surface of the circuit substrate. Thereafter, a first conductive layer and a second conductive layer are electroplated respectively over the first pads and the second pads. Afterwards, the conductive seed layer is patterned.

Abstract translation: 本发明提供一种制造电路基板的方法。 首先，提供具有第一焊盘和第二焊盘的衬底，其中第一焊盘和第二焊盘分别布置在衬底的第一表面和第二表面上。 第一焊盘电连接到第二焊盘。 接下来，在电路基板的第二表面上形成导电种子层。 此后，分别在第一焊盘和第二焊盘上电镀第一导电层和第二导电层。 之后，对导电种子层进行图案化。

公开(公告)号：US20050092518A1

公开(公告)日：2005-05-05

申请号：US11002135

申请日：2004-12-03

Applicant: Isao Matsui

Inventor： Isao Matsui

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H05K7/06 ,  H05K1/00

CPC classification number: H05K1/0271 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/0969 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A conductive film has a plurality of clearances (openings) and a plurality of auxiliary clearances. The plurality of clearances and the plurality of auxiliary clearances are formed to have such numerical apertures and locations that generate no bias in the distribution of conductive film in consideration of the entire conductive film. The conductive film can disperse stress caused by thermal expansion etc., to ease by having the plurality of clearances and the plurality of auxiliary clearances. Accordingly, the conductive film is less prone to being peeled off the insulating film. Further, since the distribution of conductive film is substantially uniform as a whole, the transfer characteristics that are fixed by the distribution become substantially uniform as a whole.

公开(公告)号：US20050056939A1

公开(公告)日：2005-03-17

申请号：US10939340

申请日：2004-09-14

Applicant: Kiyoshi Ooi ,  Tomoo Yamasaki ,  Akio Rokugawa

Inventor： Kiyoshi Ooi ,  Tomoo Yamasaki ,  Akio Rokugawa

IPC: H01G4/33 ,  H01G4/10 ,  H01G4/20 ,  H01L21/02 ,  H01L21/316 ,  H05K1/16 ,  H05K3/46 ,  H01L21/44

CPC classification number: H01L28/40 ,  H01G4/10 ,  H01G4/20 ,  H01L21/31616 ,  H01L21/31637 ,  H01L28/56 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2203/0315

Abstract: A thin-film capacitor comprising a first thin-film electrode, a second thin-film electrode, and a thin dielectric film arranged therebetween and formed of a tantalum oxide layer and an aluminum oxide layer neighboring thereto. A method of producing such a thin-film capacitor is also disclosed.

Abstract translation: 一种薄膜电容器，包括第一薄膜电极，第二薄膜电极和布置在其间的薄电介质薄膜，并由邻近的钽氧化物层和氧化铝层形成。 还公开了一种制造这种薄膜电容器的方法。

公开(公告)号：US20050029014A1

公开(公告)日：2005-02-10

申请号：US10934389

申请日：2004-09-07

Applicant: Shigeki Miura

Inventor： Shigeki Miura

IPC: H01L21/60 ,  H01L21/48 ,  H05K1/11 ,  H05K3/10 ,  H05K3/38 ,  H05K3/42 ,  B32B3/26

CPC classification number: H01L21/4846 ,  H01L21/4864 ,  H05K3/108 ,  H05K3/381 ,  H05K3/388 ,  H05K3/423 ,  H05K3/426 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2203/092 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A conductive sheet according to the present invention includes: an insulating substrate having at least one via hole, a ground conductive layer; and a top conductive layer, and characterized in that the via hole is a fine pore penetrating through the insulating substrate, the ground conductive layer is formed by a sputtering method or a vapor deposition method on all of a surface of the insulating substrate, the top conductive layer is formed on all of or part of a surface of the ground conductive layer, and the via hole is filled with the top conductive layer.

Abstract translation: 根据本发明的导电片包括：具有至少一个通孔的绝缘基底，接地导电层; 和导电层，其特征在于，所述通孔是穿过所述绝缘基板的细孔，所述接地导电层通过溅射法或气相沉积法形成在所述绝缘基板的所有表面上，所述顶部 导电层形成在接地导电层的表面的全部或一部分上，并且通孔填充有顶部导电层。