公开(公告)号：US20040246690A1

公开(公告)日：2004-12-09

申请号：US10602828

申请日：2003-06-25

Applicant: NEC Toppan Circuit Solutions, Inc. ,  NEC Tokin Corporation

Inventor： Hirofumi Nakamura ,  Satoshi Arai

IPC: H05K001/16

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/642 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/162 ,  H05K3/382 ,  H05K2201/0329 ,  H05K2201/0347 ,  H05K2201/035 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2203/0315 ,  Y10T428/24917 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A thin type printed circuit board with an enclosed capacitor of a large capacitance. The printed circuit board includes metal sheet 11 having roughed surface presenting micro-irregularities, a dielectric film for capacitor 12 covering the surface of the metal sheet, and a first electrically conductive layer of electrically conductive resin 13 covering the surface of the dielectric film. A second electrically conductive layer 14 is provided on the surface of the first electrically conductive layer in a region of via for cathode side connection 18. The metal sheet and the first and second electrically conductive layers are encapsulated by resin 15. The via for cathode side connection 18, obtained on boring through the resin 15 until reaching the second electrically conductive layer 14, is coated with an electrode 20. A via for anode side connection 19 obtained on boring through the resin 15 is coated with an electrode 21 that is insulated from the second electrically conductive layer 13 by the resin 15.

Abstract translation: 一种具有大电容的封闭电容器的薄型印刷电路板。 印刷电路板包括具有粗糙表面呈现微小凹凸的金属片11，覆盖金属片表面的电容器12的电介质膜和覆盖电介质膜表面的导电树脂13的第一导电层。 第二导电层14设置在阴极侧连接件18的通路区域中的第一导电层的表面上。金属片和第一和第二导电层被树脂15封装。阴极侧的通孔 在通过树脂15钻孔直到到达第二导电层14时获得的连接18涂覆有电极20.在通过树脂15钻孔时获得的用于阳极侧连接19的通孔涂覆有绝缘的电极21 第二导电层13由树脂15构成。

公开(公告)号：US20040238970A1

公开(公告)日：2004-12-02

申请号：US10868066

申请日：2004-06-16

Applicant: Endicott Interconnect Technologies, Inc.

Inventor： David J. Alcoe

IPC: H01L023/48

CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15312 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/116 ,  H05K3/3426 ,  H05K3/4602 ,  H05K2201/09454 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0979 ,  H05K2201/10318 ,  H01L2224/0401

Abstract: A circuitized substrate which utilizes an underlying conductive layer coupled to a pad on the substrate to assure a reinforced pad which will not be damaged or removed from the substrate when subjected to a significant load. Two or more pads can be similarly provided and coupled to the conductive layer, e.g., the layer being a common (ground) layer. An information handling system (e.g., a personal computer) utilizing the substrate is also provided.

Abstract translation: 电路化基板，其利用与基板上的焊盘耦合的下层导电层，以确保在经受显着载荷时不会损坏或从基板移除的加强垫。 可以类似地提供两个或更多个焊盘并耦合到导电层，例如该层是公共（接地）层。 还提供了利用该基板的信息处理系统（例如个人计算机）。

公开(公告)号：US20040201096A1

公开(公告)日：2004-10-14

申请号：US10812349

申请日：2004-03-30

Inventor： Tomoo Iijima ,  Kimitaka Endo ,  Kazuo Ikenaga ,  Hiroshi Odaira ,  Naoto Minari ,  Takashi Kato

IPC: H01L023/48

CPC classification number: H05K1/115 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5387 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H05K1/0393 ,  H05K1/113 ,  H05K1/167 ,  H05K3/06 ,  H05K3/062 ,  H05K3/108 ,  H05K3/3457 ,  H05K3/363 ,  H05K3/4038 ,  H05K3/4617 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49213 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: An object of the present invention is to reduce the number of steps necessary for connecting between a wiring circuit board and a printed circuit board and to achieve a low-cost wiring circuit board. A wiring circuit board (2) includes an insulating film (4), a bump (6), an etching barrier layer (8), and a wiring layer (10). The bump (6) is made of copper and formed to penetrate through the insulating film (4). A top face of the bump (6) is exposed at a surface of the insulating film (4) flush therewith. The etching barrier layer (8) is made of nickel (Ni) and formed underneath the bump (6). The bump (6) is connected to the wiring layer (10) through the etching barrier layer (8). A solder ball (12) is formed on the top face of the bump (6). A printed circuit board (14) as a rigid board is connected to the wiring circuit board (2). A wiring layer (16) is connected to the bump (6) through the solder ball (12) to thereby mount the wiring circuit board (2) to the printed circuit board (14).

Abstract translation: 本发明的一个目的是减少连接布线电路板和印刷电路板所需的步骤数量并实现低成本布线电路板。 布线电路板（2）包括绝缘膜（4），凸块（6），蚀刻阻挡层（8）和布线层（10）。 凸块（6）由铜制成并穿透绝缘膜（4）。 凸起（6）的顶面在与其齐平的绝缘膜（4）的表面露出。 蚀刻阻挡层（8）由镍（Ni）制成并形成在凸块（6）的下方。 凸块（6）通过蚀刻阻挡层（8）与布线层（10）连接。 在凸块（6）的顶面上形成焊球（12）。 作为刚性基板的印刷电路板（14）连接到布线电路板（2）。 布线层（16）通过焊球（12）与突起（6）连接，从而将布线电路板（2）安装到印刷电路板（14）上。

公开(公告)号：US06802120B2

公开(公告)日：2004-10-12

申请号：US10191986

申请日：2002-07-10

Applicant: Toshiki Uehara

Inventor： Toshiki Uehara

IPC: H05K310

CPC classification number: H05K1/112 ,  H05K1/18 ,  H05K3/4069 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/035 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10189 ,  H05K2201/1059 ,  H05K2203/1572 ,  Y10S29/016 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method of manufacturing a printed wiring board, enabling insertion components to be mounted on both sides thereof, including: a) providing first and second copper-clad laminates, including plated through-holes thereon; b) hot-pressing the laminates with each other and a first prepreg bonding sheet therebetween, so that the through-holes are closed by the prepreg to form non-through holes; c) laminating a second prepreg on each of the surfaces of the composite laminate; d) covering the opening of respective non-through holes with a heat resistant resin film; e) laminating one-side copper-clad laminate on each of the surfaces of the product of (d), with the copper side out, followed by hot-pressing; f) etching the copper sides to form outer layer circuit patterns; g) removing the base material layers covering the openings of the non-through holes; and h) removing the heat resistant resin films of the openings of the non-through holes.

Abstract translation: 一种制造印刷电路板的方法，其能够在两侧安装插入部件，包括：a）提供第一和第二铜包覆层压板，其上包括镀覆的通孔; b）将层叠体彼此热压，并在其间进行第一预浸料接合片，使得通孔被预浸料坯封闭以形成非通孔; c）在复合层压板的每个表面上层压第二预浸料; d）用耐热树脂膜覆盖各个非通孔的开口; e）在（d）的产品的每个表面上层叠一面覆铜层压板，将铜侧排出，然后热压; f）蚀刻铜边以形成外层电路图案; g）去除覆盖非通孔的开口的基材层; 以及h）去除非通孔的开口的耐热树脂膜。

公开(公告)号：US20040192039A1

公开(公告)日：2004-09-30

申请号：US10397426

申请日：2003-03-27

Applicant: E Touch Corporation

Inventor： Te-Yeu Su ,  Hsin-Herng Wang ,  Chien-Chang Huang ,  Yu-Chou Yeh

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H05K1/167 ,  H05K1/095 ,  H05K3/4623 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2203/1453

Abstract: A method of fabricating multi-layer circuit structure with embedded polymer resistors comprises forming a plurality of electrically conductive paths on a first substrate, forming polymer resistor paste between first and second of the electrically conductive paths on the first substrate, curing the polymer resistor paste by exposure to ultraviolet radiation to thereby solidify the shape of the polymer resistor paste, heating the polymer resistor paste to produce a first resistor, forming a plurality of electrically conductive paths on a second substrate, bonding the first and second substrates with an adhesive, wherein the first resistor is positioned between the first and second substrates.

Abstract translation: 一种制造具有嵌入式聚合物电阻器的多层电路结构的方法包括在第一衬底上形成多个导电路径，在第一衬底上的第一和第二导电路径之间形成聚合物电阻浆料，将聚合物电阻膏固化 暴露于紫外线辐射，从而固化聚合物电阻膏的形状，加热聚合物电阻膏以产生第一电阻，在第二基底上形成多个导电路径，用粘合剂粘合第一和第二基底，其中 第一电阻器位于第一和第二基板之间。

公开(公告)号：US20040159921A1

公开(公告)日：2004-08-19

申请号：US10775736

申请日：2004-02-10

Inventor： Stephen Moxham ,  William Stephenson

IPC: H01L021/44 ,  H01L023/495

CPC classification number: H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method and apparatus for supporting a microelectronic substrate. The apparatus can include a microelectronic substrate and a support member carrying the microelectronic substrate. The apparatus can further include a first connection structure carried by the support member. The first connection structure can have a first bond site configured to receive a flowable conductive material, and can further have at least two first elongated members connected and extending outwardly from the first bond site. Each first elongated member can be configured to receive at least a portion of the flowable conductive material from the first bond site, with none of the first elongated members being electrically coupled to the microelectronic substrate. The assembly can further include a second connection structure that is electrically coupled to the microelectronic substrate and that can include second elongated members extending away from a second bond site. The number of second elongated members can be equal to the number of first elongated members.

Abstract translation: 一种用于支撑微电子衬底的方法和装置。 该装置可以包括微电子衬底和承载微电子衬底的支撑构件。 该装置还可以包括由支撑构件承载的第一连接结构。 第一连接结构可以具有构造成接收可流动的导电材料的第一接合位置，并且还可以具有连接并从第一接合位置向外延伸的至少两个第一细长构件。 每个第一细长构件可以被构造成从第一接合位置接收可流动的导电材料的至少一部分，而第一细长构件没有一个电耦合到微电子衬底。 组件还可以包括电耦合到微电子衬底的第二连接结构，并且可以包括远离第二接合位置延伸的第二细长构件。 第二细长构件的数量可以等于第一细长构件的数量。

公开(公告)号：US20040136168A1

公开(公告)日：2004-07-15

申请号：US10407460

申请日：2003-04-07

Inventor： Guy M.A.F. Duxbury ,  Aneta Wyrzykowska ,  Luigi G. Difilippo ,  Herman Kwong

IPC: H02H003/00

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734 ,  Y10T29/49016 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Techniques for reducing the number of layers in a multilayer signal routing device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method wherein the multilayer signal routing device has a plurality of electrically conductive signal path layers for routing a plurality of electrical signals thereon. The method may comprise forming a plurality of electrically conductive vias in the multilayer signal routing device for electrically connecting at least two of the plurality of electrically conductive signal path layers, wherein the plurality of vias are arranged so as to form at least one channel in at least one other of the plurality of electrically conductive signal path layers. The method may also comprise grouping at least a portion of the plurality of electrical signals based at least in part upon their proximity to the at least one channel so that they may be efficiently routed therein.

Abstract translation: 公开了用于减少多层信号路由设备中的层数的技术。 在一个特定的示例性实施例中，这些技术可以被实现为一种方法，其中多层信号路由设备具有用于在其上路由多个电信号的多个导电信号路径层。 所述方法可以包括在所述多层信号路由设备中形成多个导电通孔，用于电连接所述多个导电信号路径层中的至少两个，其中所述多个通孔被布置成在其中形成至少一个通道 多个导电信号路径层中的至少另一个。 该方法还可以包括至少部分地基于它们与至少一个信道的接近度来分组多个电信号的至少一部分，使得它们可以被有效地路由到其中。

公开(公告)号：US20040134682A1

公开(公告)日：2004-07-15

申请号：US10751428

申请日：2004-01-06

Applicant: IBIDEN CO., LTD.

Inventor： Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

IPC: H05K001/00

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing. The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

Abstract translation: 本发明的目的是提供一种制造多层印刷电路板的方法，其能够同时通孔填充和形成导体电路，并且可以在基板和高密度布线上构造具有良好结晶度和均匀沉积的通孔 并且可以实现高可靠性的导体连接而不退火。 本发明涉及一种多层印刷电路板的制造方法，其特征在于，在形成有导体电路的基板上设置层间树脂绝缘层，在所述层间树脂绝缘层上形成用于形成通孔的开口，形成无电镀金属 层，在其上设置抗蚀剂，进行电镀，剥离抗蚀剂并蚀刻无电镀金属层以提供导体电路和通孔，其中使用所述无电镀金属层作为阴极间歇地进行电镀 以及在所述阳极和所述阴极之间的恒定电压下的电镀金属作为阳极。

公开(公告)号：US20040129453A1

公开(公告)日：2004-07-08

申请号：US10337949

申请日：2003-01-07

Inventor： David W. Boggs ,  Daryl Sato ,  John Dungan

IPC: H05K001/11 ,  H01R012/04

CPC classification number: H05K1/112 ,  H05K3/4076 ,  H05K3/421 ,  H05K2201/09245 ,  H05K2201/09472 ,  H05K2201/09509

Abstract: Embodiments of substrate in accordance with the present invention provide interconnect cavities for direct interconnection between SMT components and internal conductive inner layers, as well as surface outer layers. Interconnect cavities eliminate the need for through hole vias and require less substrate surface area and internal volume. Each interconnect cavity comprises a cavity extending from the substrate surface to an adjacent internal conductive inner layer directly beneath the cavity. The cavity extends through a conductive outer layer on the substrate surface. The cavity has a conductive liner interconnected with the outer layer and the inner layer forming a cup-shaped conductive depression interconnecting the outer layer with the inner layer.

Abstract translation: 根据本发明的衬底的实施例提供用于SMT部件和内部导电内层之间以及表面外层的直接互连的互连腔。 互连腔消除了对通孔的需要，并且需要较少的衬底表面积和内部体积。 每个互连腔包括从衬底表面延伸到空腔正下方的相邻内部导电内层的空腔。 空腔延伸穿过衬底表面上的导电外层。 空腔具有与外层互连的导电衬垫，内层形成将外层与内层互连的杯形导电凹部。

公开(公告)号：US06760208B1

公开(公告)日：2004-07-06

申请号：US10331901

申请日：2002-12-30

Applicant: Thomas D. Nagode ,  Gregory Redmond Black

Inventor： Thomas D. Nagode ,  Gregory Redmond Black

IPC: H02H700

CPC classification number: H01P5/02 ,  H01L27/0805 ,  H05K1/0237 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09727

Abstract: A distributive capacitor 205 and impedance matching network 201 and transmitter 101 that use the capacitor and are suitable for high density integration applications include a printed circuit substrate 303 comprising one of a printed circuit board and a silicon based substrate, a first conductive layer 305 disposed on the printed circuit substrate, a layer of dielectric material 307 disposed on the first conductive layer and having a thickness, the dielectric material having a dielectric constant more than five times greater than the dielectric constant of the printed circuit substrate; and a second conductive layer 309 disposed on the layer of dielectric material and having a second length 311 and a second width 603 that are selected so that the distributive capacitor operates as a transmission line.

Abstract translation: 使用该电容器并适用于高密度集成应用的分配电容器205和阻抗匹配网络201以及发射机101包括印刷电路基板303，其包括印刷电路板和硅基基板之一，第一导电层305设置在 印刷电路基板，设置在第一导电层上并具有厚度的电介质材料层307，介电材料的介电常数大于印刷电路基板的介电常数的五倍以上; 以及设置在介电材料层上并具有第二长度311和第二宽度603的第二导电层309，第二长度311和第二宽度603被选择成使得分配电容器作为传输线工作。