公开(公告)号：US09123763B2

公开(公告)日：2015-09-01

申请号：US13271952

申请日：2011-10-12

申请人： Chen-Hua Yu ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Ming-Da Cheng ,  Chih-Wei Lin

发明人： Chen-Hua Yu ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Ming-Da Cheng ,  Chih-Wei Lin

IPC分类号： H01L23/48 ,  H01L21/683 ,  H01L23/538 ,  H01L21/56 ,  H01L25/10 ,  H01L21/36 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H05K1/18 ,  H01L23/498

CPC分类号： H01L25/50 ,  H01L21/31051 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/185 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/48

摘要： A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.

摘要翻译： 封装封装（PoP）结构包括第一封装和第二封装。 第一包装包括第一模具，第二模具和芯材料。 芯材料具有第一表面和第二表面。 第一再分配层（RDL）位于第一表面上，第二RDL位于第二表面上。 第一模具设置在第一表面和第二表面之间的芯材料中。 第二管芯耦合到第一RDL和第二RDL之一。 第二包装包括第三管芯和插入件。 插入器具有第一侧和第二侧。 第三裸片耦合到插入器的第二侧。 第一封装通过耦合到插入件的第二侧和第一RDL的第一电连接器耦合到第二封装。

公开(公告)号：US08716858B2

公开(公告)日：2014-05-06

申请号：US13167946

申请日：2011-06-24

申请人： Chen-Fa Lu ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Chen-Fa Lu ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： H01L23/48

CPC分类号： H01L24/03 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05583 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device includes a barrier layer between a solder bump and a post-passivation interconnect (PPI) layer. The barrier layer is formed of at least one of an electroless nickel (Ni) layer, an electroless palladium (Pd) layer or an immersion gold (Au) layer.

摘要翻译： 半导体器件包括在焊料凸块和钝化后互连（PPI）层之间的阻挡层。 阻挡层由无电镀镍（Ni）层，无电解钯（Pd）层或浸金（Au）层中的至少一种形成。

公开(公告)号：US08664040B2

公开(公告)日：2014-03-04

申请号：US13331061

申请日：2011-12-20

申请人： Chen-Hua Yu ,  Chung-Shi Liu ,  Chun-Cheng Lin ,  Meng-Tse Chen ,  Ming-Da Cheng

发明人： Chen-Hua Yu ,  Chung-Shi Liu ,  Chun-Cheng Lin ,  Meng-Tse Chen ,  Ming-Da Cheng

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/31 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/14 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

摘要： A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed.

摘要翻译： 一种方法包括对包装进行蚀刻步骤。 该包装包括包装部件，在包装部件的顶表面上的连接器，结合到包装部件的顶表面的管芯，以及模制在包装部件的顶表面上的模制材料。 成型材料覆盖连接器，其中通过蚀刻步骤去除覆盖连接器的成型材料的一部分，并且连接器被暴露。

公开(公告)号：US20130167373A1

公开(公告)日：2013-07-04

申请号：US13527459

申请日：2012-06-19

申请人： Chien Ling Hwang ,  Yeong-Jyh Lin ,  Yi-Li Hsiao ,  Ming-Da Cheng ,  Tsai-Tsung Tsai ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Chien Ling Hwang ,  Yeong-Jyh Lin ,  Yi-Li Hsiao ,  Ming-Da Cheng ,  Tsai-Tsung Tsai ,  Chung-Shi Liu ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： B26D7/27 ,  H01R43/00

CPC分类号： H01L24/11 ,  H01L21/4853 ,  H01L24/13 ,  H01L24/78 ,  H01L2224/056 ,  H01L2224/1111 ,  H01L2224/1134 ,  H01L2224/13005 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/451 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48 ,  H01L2224/7855 ,  H01L2224/78621 ,  H01L2224/85051 ,  H01L2224/854 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/206 ,  Y10T29/49192 ,  Y10T29/49213 ,  Y10T29/514 ,  Y10T29/5177 ,  Y10T29/53217 ,  Y10T29/53235 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01049 ,  H01L2224/4554

摘要： An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump.

公开(公告)号：US20130134588A1

公开(公告)日：2013-05-30

申请号：US13397747

申请日：2012-02-16

申请人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Chung-Shi Liu ,  Ming-Da Cheng

发明人： Chen-Hua Yu ,  Mirng-Ji Lii ,  Chung-Shi Liu ,  Ming-Da Cheng

IPC分类号： H01L23/498

CPC分类号： H01L25/0657 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/038 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05693 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/1184 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1358 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48693 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48793 ,  H01L2224/48811 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48893 ,  H01L2224/73204 ,  H01L2224/81009 ,  H01L2224/81026 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/01029 ,  H01L2924/01006

摘要： Package-On-Package (PoP) structures and methods of forming PoP structures are disclosed. According to an embodiment, a structure comprises a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.

摘要翻译： 封装封装（PoP）结构和形成PoP结构的方法被公开。 根据实施例，一种结构包括第一基板，螺柱灯泡，模具，第二基板和电连接器。 螺柱灯泡耦合到第一基板的第一表面。 模具附接到第一基板的第一表面。 电连接器耦合到第二基板，并且相应的电连接器耦合到相应的螺柱灯泡。

公开(公告)号：US08440562B2

公开(公告)日：2013-05-14

申请号：US12881939

申请日：2010-09-14

申请人： Chung-Shi Liu ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L21/44

CPC分类号： H01L23/53295 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germanide nitride layer over the conductive wiring.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的第一电介质层; 第一电介质层中的导电布线; 以及导电布线上的锗锗化锗氮化物层。

公开(公告)号：US20120211547A1

公开(公告)日：2012-08-23

申请号：US13031040

申请日：2011-02-18

申请人： Yi-Li Hsiao ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chien Ling Hwang

发明人： Yi-Li Hsiao ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chien Ling Hwang

IPC分类号： B23K1/20 ,  B23K3/08

CPC分类号： B23K1/203 ,  B23K3/082

摘要： A flux dipping apparatus includes a flux plate having a top surface; and a dipping cavity in the flux plate and recessed from the top surface. A flux leveler is disposed over the flux plate and configured to move parallel to the top surface. A piezoelectric actuator is configured to adjust a distance between the flux leveler and the top surface in response to a controlling voltage applied to electrodes of the first piezoelectric actuator.

摘要翻译： 焊剂浸渍装置包括具有顶表面的焊剂板; 以及在焊剂板中的浸入腔并且从顶表面凹陷。 助熔剂矫正器设置在焊剂板上方并且被配置成平行于顶表面移动。 压电致动器被配置为响应于施加到第一压电致动器的电极的控制电压来调节通量调节器和顶表面之间的距离。

公开(公告)号：US20120028441A1

公开(公告)日：2012-02-02

申请号：US13269260

申请日：2011-10-07

申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Yuh-Jier Mii ,  Yuan-Chen Sun

发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Yuh-Jier Mii ,  Yuan-Chen Sun

IPC分类号： H01L21/762

CPC分类号： H01L21/50 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/762 ,  H01L21/76898 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/05553 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.

摘要翻译： 一种用于制造3D（三维）SIC（堆叠集成芯片）半导体器件的方法和系统。 该系统包括真空室，真空环境处理室和粘合室，尽管在一些实施例中，相同的物理外壳可以用于这些功能中的一种以上。 与真空环境处理室连通的真空环境处理源提供基于氢（H 2）的热退火，基于H 2的等离子体处理或基于氨（NH 3）的等离子体处理中的一种或多种。 在另一个实施例中，一种方法包括将半导体芯片放置在真空环境中，执行所选择的真空环境处理，以及将芯片接合到基底晶片。 在半导体晶片上形成为多个芯片的多个芯片当然可以在切割之前或之后以这种方式同时进行处理和粘合。

公开(公告)号：US08048717B2

公开(公告)日：2011-11-01

申请号：US11789617

申请日：2007-04-25

申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Yuh-Jier Mii ,  Yuan-Chen Sun

发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Yuh-Jier Mii ,  Yuan-Chen Sun

IPC分类号： H01L21/00

CPC分类号： H01L21/50 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/762 ,  H01L21/76898 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/05553 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.

摘要翻译： 一种用于制造3D（三维）SIC（堆叠集成芯片）半导体器件的方法和系统。 该系统包括真空室，真空环境处理室和粘合室，尽管在一些实施例中，相同的物理外壳可以用于这些功能中的一种以上。 与真空环境处理室连通的真空环境处理源提供基于氢（H 2）的热退火，基于H 2的等离子体处理或基于氨（NH 3）的等离子体处理中选择的一种或多种。 在另一个实施例中，一种方法包括将半导体芯片放置在真空环境中，执行所选择的真空环境处理，以及将芯片接合到基底晶片。 在半导体晶片上形成为多个芯片的多个芯片当然可以在切割之前或之后以这种方式同时进行处理和粘合。

公开(公告)号：US20110121410A1

公开(公告)日：2011-05-26

申请号：US13015328

申请日：2011-01-27

申请人： Chung-Shi Liu ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L29/78 ,  H01L23/532

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76856 ,  H01L23/485 ,  H01L29/665 ,  H01L29/7833

摘要： System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.

摘要翻译： 提供了降低接触电阻和改善阻隔性能的系统和方法。 一个实施例包括介电层和延伸穿过电介质层的连接到导电区域的触点。 在通过用于接触的电介质层形成开口之后，在导电区域和触点之间通过无电解电镀导电区域形成接触阻挡层。 然后处理接触阻挡层以填充接触阻挡层的晶界，从而提高接触电阻。 在另一个实施例中，接触阻挡层通过在形成电介质层之前的无电镀形成在导电区上。